Downlink Receiver Adjacent Channel Selectivity Test

Introduction

TDSCDMA_DnLnk_RX_ACS test bench for TD-SCDMA downlink (base station to user equipment) receiver adjacent channel selectivity testing provides a way for users to connect to an RF circuit device under test (RF DUT) and determine its ACS performance by BER measurements.

ACS is a measure of a receiver's ability to receive a wanted signal at its assigned channel frequency in the presence of an adjacent channel signal. ACS is the ratio of the receiver filter attenuation on the assigned channel frequency to the receiver filter attenuation on the adjacent channel frequency.

The signal and measurements in this test bench are designed according to 3GPP TS 34.122 section 6.4.

This TD-SCDMA signal source model is compatible with Agilent Signal Studio software option 411. Details regarding Signal Studio for TD-SCDMA are included at the website http://www.agilent.com/find/signalstudio.

This test bench includes a TX DSP section, an RF modulator, RF output source resistance, an RF DUT connection, RF receivers, and DSP measurement blocks as illustrated in Receiver Wireless Test Bench Block Diagram. The generated test signal is sent to the DUT.

Receiver Wireless Test Bench Block Diagram

The TD-SCDMA RF power delivered into a matched load is the average power delivered in the selected time slot TS0 in the TD-SCDMA subframe. TD-SCDMA Downlink Envelope for RF Signal shows the RF envelope for an output signal with -91 dBm power.

TD-SCDMA Downlink Envelope for RF Signal

Test Bench Basics

A template is provided for this test bench.

TDSCDMA Downlink Receiver ACS Test Bench

To access the template:

1. In an Analog/RF schematic window select Insert > Template.
2. In the Insert > Template dialog box, choose TDSCDMA_DnLnk_RX_ACS_test , click OK ; click left to place the template in the schematic window.

An example design using this template is available; from the ADS Main window click File > Example Project > TDSCDMA > TDSCDMA_RF_Verification_prj > TDSCDMA_DnLnk_RX_ACS _test.dsn.

The basics for using the test bench are:

• Replace the DUT (Amplifier2 is provided with this template) with an RF DUT that is suitable for this test bench.
• CE_TimeStep, FSource, SourcePower, and FMeasurement parameter default values are typically accepted; otherwise, set values based on your requirements.
• Run the simulation and view Data Display page(s) for your measurement(s).

For details, refer to Test Bench Details.

Test Bench Details

The following sections provide details for setting up a test bench, setting measurement parameters for more control of the test bench, simulation measurement displays, and baseline performance.
Open and use the TDSCDMA_DnLnk_RX_ACS_test template:

1. In an Analog/RF schematic window select Insert > Template.
2. In the Insert > Template dialog box, choose TDSCDMA_DnLnk_RX_ACS_test , click OK ; click left to place the template in the schematic window.

The test bench setup is detailed here.

1. Replace the DUT (Amplifier2 is provided with this template) with an RF DUT that is suitable for this test bench.
   For information regarding using certain types of DUTs, see Appendix A, RF DUT Limitations.
2. Set the Required Parameters .

   Note Refer to TDSCDMA_DnLnk_RX_ACS for a complete list of parameters for this test bench.

   Generally, default values can be accepted; otherwise, values can be changed by the user as needed.

• Set CE_TimeStep.
  Cosimulation occurs between the test bench (using ADS Ptolemy Data Flow simulation technology) and the DUT (using Circuit Envelope simulation technology). Each technology requires its own simulation time step with time-step coordination occurring in the interface between the technologies.
  CE_TimeStep defines the Circuit Envelope simulation time step to be used with this DUT. The CE_TimeStep must be set to a value equal to or a submultiple of (less than) WTB_TimeStep; otherwise, simulation will stop and an error message will be displayed.
  Note that WTB_TimeStep is not user-settable. Its value is derived from other test bench parameter values; with default settings WTB_TimeStep= 97.65625 nsec. The value is displayed in the Data Display pages as TimeStep.
  WTB_TimeStep = 1/(ChipRate × SamplesPerChip)
  where
  ChipRate is 1.28MHz
  SamplesPerChip is the number of samples per chip
  • Set FSource, SourcePower, and FMeasurement.
    • FSource defines the RF frequency for the TD-SCDMA signal input to the RF DUT.
    • SourcePower defines the power level for FSource. SourcePower is defined as the average power during the non-idle time of the TD-SCDMA signal segment.
    • FMeasurement defines the RF frequency output from the RF DUT to be measured.

1. More control of the test bench can be achieved by setting parameters on the Basic Parameters , Signal Parameters , and the measurement categories. For details, refer to Setting Parameters.
2. The RF modulator (shown in the block diagram in Receiver Wireless Test Bench Block Diagram) uses FSource, SourcePower ( Required Parameters ), MirrorSourceSpectrum ( Basic Parameters) , GainImbalance, PhaseImbalance, I_OriginOffset, Q_OriginOffset, and IQ_Rotation ( Signal Parameters ).
   The RF output resistance uses SourceR and SourceTemp ( Basic Parameters ). The RF output signal source has a 50-ohm (default) output resistance defined by SourceR.
   RF output (and input to the RF DUT) is at the frequency specified (FSource), with the specified source resistance (SourceR) and with power (SourcePower) delivered into a matched load of resistance SourceR. The RF signal has additive Gaussian noise power set by resistor temperature (SourceTemp).
   Note that the Meas_in point of the test bench provides a resistive load to the RF DUT set by the MeasR value (50-ohm default) ( Basic Parameters ).
   The Meas signal contains linear and nonlinear signal distortions and time delays associated with the RF DUT input to output characteristics.
   The DSP block (shown in the block diagram in Receiver Wireless Test Bench Block Diagram) uses other Signal Parameters .
3. More control of Circuit Envelope analysis can be achieved by setting Envelope controller parameters. These settings include Enable Fast Cosim, which may speed the RF DUT simulation more than 10×. Setting these simulation options is described in Setting Fast Cosimulation Parameters and Setting Circuit Envelope Analysis Parameters in the Wireless Test Bench Simulation documentation.
4. To run a simulation, choose Simulate > Simulate in the Schematic window.
   For details on Running a Simulation refer to the Wireless Test Bench Simulation documentation.
5. Simulation results will appear in a Data Display window for each measurement. Simulation Measurement Displays describes results for each measurement available for this test bench.

For details on Viewing Results refer to the W ireless Test Bench Simulation documentation.