Downlink Transmitter Test

Introduction

TDSCDMA_DnLnk_TX text bench for TDSCDMA downlink (base station to user equipment) transmitter testing provides a way for users to connect to an RF circuit device under test (RF DUT) and determine its performance by activating various measurements. This test bench provides signal measurements for RF envelope, constellation, power (including power vs. time and CCDF), spectrum, and EVM.

The signal and most of the measurements are designed according to 3GPP TS 25 (Release 4).

This TD-SCDMA signal source model is compatible with Agilent Signal Studio software option 411. Details regarding Signal Studio for TD-SCDMA are included at the website http://www.agilent.com/find/signalstudio.

The DUT output signal can be sent to an Agilent ESG RF signal generator.

This test bench includes a DSP section, an RF modulator, RF output source resistance, RF DUT connection, RF receivers, and DSP measurement blocks, as illustrated in Transmitter Wireless Test Bench Block Diagram. The generated test signal is sent to the DUT.

Transmitter Wireless Test Bench Block Diagram

The downlink channel subframe structure is illustrated in 12.2 kbps Downlink Channel Subframe Structure. One frame consists of two subframes. Each subframe consists of 7 time slots (TS), and one downlink pilot time slot (DwPTS), one guard period (GP) and one uplink pilot time slot (UpPTS). Each time slot can transmit DPCH signals. One subframe consists of 6400 chips. Because the chip rate is 1.28 MHz, the subframe has a 5 msec duration.

In the example in 12.2 kbps Downlink Channel Subframe Structure, two DPCH signals in DPCH1 and DPCH2 are transmitted in TS0. The first DPCH bits are modulated by QPSK and spread by Walsh code of length 16 then transmitted in the slot. The DPCH1 signal is composed of 88 coded information bits (88 × 16/2 chips) and 144 chips for midamble sequence plus 16 chips for GP. The DPCH2 signal, with the same modulation and spread scheme as DPCH1, is composed of 76 coded information bits (76 × 16/2 chips), 8 bits (8 × 16/2 chips) for transport format combination indicator (TFCI), 144 chips for midamble sequence, 4 bits (4 × 16/2 chips) for transmitter power control and synchronization shift (TPC and SS) plus 16 chips for GP. The total chips for the subframe is composed of 7 time slots plus 96 chips for DwPTS, 96 chips for GP and 160 chips for UpPTS and summarized as (88 × 8+144+16) × 7+160+96 × 2=6400 chips.

12.2 kbps Downlink Channel Subframe Structure

TD-SCDMA RF power delivered into a matched load is the average power delivered in the selected time slot TS2 in the TD-SCDMA subframe. RF Signal Downlink Envelope shows the RF envelope for an output signal with 30 dBm power.

RF Signal Downlink Envelope

Test Bench Basics

A template is provided for this test bench.

TDSCDMA Downlink Transmitter Test Bench

To access the template:

1. In an Analog/RF schematic window select Insert > Template.
2. In the Insert > Template dialog box, choose TDSCDMA_DnLnk_TX_test , click OK ; click left to place the template in the schematic window.

An example design using this template is available; from the ADS Main window click File > Example Project > TDSCDMA > TDSCDMA_RF_Verification_prj > TDSCDMA_DnLnk_TX_test.dsn.

The basics for using the test bench are:

• Replace the DUT (Amplifier2 is provided with this template) with an RF DUT that is suitable for this test bench.
• CE_TimeStep, FSource, SourcePower, and FMeasurement parameter default values are typically accepted; otherwise, set values based on your requirements.
• Activate/deactivate measurements based on your requirements.
• Run the simulation and view Data Display page(s) for your measurement(s).

For details, refer to Test Bench Details.

Test Bench Details

The following sections provide details for setting up a test bench, setting measurement parameters for more control of the test bench, simulation measurement displays, and baseline performance.
Open and use the TDSCDMA_DnLnk_TX template:

1. In an Analog/RF schematic window select Insert > Template.
2. In the Insert > Template dialog box, choose TDSCDMA_DnLnk_TX_test , click OK ; click left to place the template in the schematic window.

Test bench setup is detailed here.

1. Replace the DUT (Amplifier2 is provided with this template) with an RF DUT that is suitable for this test bench.
   For information regarding using certain types of DUTs, see Appendix A, RF DUT Limitations.
2. Set the Required Parameters

   Note Refer to TDSCDMA_DnLnk_TX for a complete list of parameters for this test bench.

   Generally, default values can be accepted; otherwise, values can be changed by the user as needed.

   • Set CE_TimeStep.
     Cosimulation occurs between the test bench (using ADS Ptolemy Data Flow simulation technology) and the DUT (using Circuit Envelope simulation technology). Each technology requires its own simulation time step with time-step coordination occurring in the interface between the technologies.
     CE_TimeStep defines the Circuit Envelope simulation time step to be used with this DUT. The CE_TimeStep must be set to a value equal to or a submultiple of (less than) WTB_TimeStep; otherwise, simulation will stop and an error message will be displayed.
     Note that WTB_TimeStep is not user-settable. Its value is derived from other test bench parameter values; with default settings WTB_TimeStep= 97.65625 nsec. The value is displayed in the Data Display pages as TimeStep.
     WTB_TimeStep = 1/(ChipRate × SamplesPerChip)
     where
     ChipRate is 1.28MHz
     SamplesPerChip is the number of samples per chip
   • Set FSource, SourcePower, and FMeasurement.
     • FSource defines the RF frequency for the TD-SCDMA signal input to the RF DUT.
     • SourcePower defines the power level for FSource. SourcePower is defined as the average power during the non-idle time of the TD-SCDMA signal segment.
     • FMeasurement defines the RF frequency output from the RF DUT to be measured.
3. Activate/deactivate ( YES / NO ) test bench measurements (refer to TDSCDMA_DnLnk_TX). At least one measurement must be enabled:
   • • RF_EnvelopeMeasurement
     • Constellation
     • PowerMeasurement
     • SpectrumMeasurement
     • EVM_Measurement
4. More control of the test bench can be achieved by setting parameters in the Basic Parameters , Signal Parameters , and measurement categories for each activated measurement. For details, refer to Setting Parameters. The RF modulator (shown in the block diagram in Transmitter Wireless Test Bench Block Diagram) uses FSource, SourcePower ( Required Parameters ), MirrorSourceSpectrum ( Basic Parameters) , GainImbalance, PhaseImbalance, I_OriginOffset, Q_OriginOffset, and IQ_Rotation ( Signal Parameters ).
   The RF output resistance uses SourceR, SourceTemp, and EnableSourceNoise ( Basic Parameters ). The RF output signal source has a 50-ohm (default) output resistance defined by SourceR.
   RF output (and input to the RF DUT) is at the frequency specified (FSource), with the specified source resistance (SourceR) and with power (SourcePower) delivered into a matched load of resistance SourceR. The RF signal has additive Gaussian noise power set by resistor temperature (SourceTemp) (when EnableSourceNoise=YES).
   Note that the Meas_in point of the test bench provides a resistive load to the RF DUT set by the MeasR value (50-ohm default) ( Basic Parameters ).
   The Meas signal contains linear and nonlinear signal distortions and time delays associated with the RF DUT input to output characteristics.
   The TX DSP block (shown in the block diagram in Transmitter Wireless Test Bench Block Diagram) uses other Signal Parameters .
5. More control of Circuit Envelope analysis can be achieved by setting Envelope controller parameters. These settings include Enable Fast Cosim, which may speed the RF DUT simulation more than 10×. Setting these simulation options is described in Setting Fast Cosimulation Parameters and Setting Circuit Envelope Analysis Parameters in the Wireless Test Bench Simulation documentation.
6. To send the RF DUT output signal to an Agilent ESG RF signal generator, set parameters on the Signal to ESG category.
   For details, refer to Signal to ESG Parameters.
7. To run a simulation, choose Simulate > Simulate in the Schematic window.
   For details on Running a Simulation refer to the Wireless Test Bench Simulation documentation.
8. Simulation results will appear in a Data Display window for each measurement. Simulation Measurement Displays describes results for each measurement available for this test bench.

For details on Viewing Results refer to the Wireless Test Bench Simulation documentation.