Troubleshooting a DC Simulation

This section presents suggestions for using this simulator and improving the accuracy of results.

The robustness and speed of the default DC analysis algorithm has been significantly improved in ADS 2005A. All DC analyses with factory-default settings are expected to converge to the correct solution with near-optimal speed. This means that it is extremely unlikely that any of the following advanced simulation parameters must be altered:

ConvMode	ArcMaxStep
MaxDeltaV	ArcLevelMaxStep
MaxIters	ArcMinValue
MaxStepRatio	ArcMaxValue
MaxShrinkage	LimitingMode

Note As a result of the improvements made to the DC simulation algorithm, it is extremely unlikely that the factory-default values for the advanced simulation parameters need to be modified. You are strongly encouraged to leave these parameters set to their default values. If you encounter a circuit for which a DC analysis does not converge using the default values, or you find it necessary to change the value of any of these parameters, please contact Agilent EEsof Technical Support. See Defining Advanced Simulation Parameters for details about these parameters.

Use the following checklist to locate and fix problems. For details about specific problems, see the sections that follow.

• Use the simulator Options to turn on Issue warnings ( GiveAllWarnings=yes ) and increase Maximum number of warnings ( MaxWarnings=10 by default). To set these parameters in ADS, place the Options component on your schematic from the Simulation-DC palette. For details about simulator options, see Using the Simulator Options Component.
• Read all error and warning messages from the Simulation/Synthesis Messages window and make corrections accordingly.
• Read all status information from the Status/Summary window (select Show Complete Status Message under Window tab) and make corrections accordingly.
• Check your setup for common errors (see Common Setup Errors).
• Loosen the simulation Options parameters for absolute and/or relative simulation tolerances (see Adjusting Tolerance Parameters).
• Turn on/off the Topology Checker (on by default) using the simulation Options parameters (see Topology Check and Correction).
• Check if you have created a circuit with no solution (see Impossible Circuits).
• Check if Imax should be increased (see Model Parameter Imax is Too Small).

Common Setup Errors

If your circuit does not converge, or if it converges but your DC I-V curves appear different than expected, it can be due to one or more of the following reasons:

• Check component and model parameter values and units, especially small series resistor values in model parameters.
• Check if your independent swept parameters are swapped on the grid display. For example, if SRC1 sweeps a transistor gate voltage and SRC2 sweeps a drain voltage, and if the current is displayed with SRC1 (gate voltage) on the x-axis, these traces will not look like typical DC I-V traces. Exchange the order of the swept variables SRC1 and SRC2 on the grid.
• Check if you are sweeping one source with large variations and another with small variations. For example, say that you are sweeping the base current and the collector voltage of a transistor by connecting a DC current source at the base and a DC voltage source at the collector. Furthermore, say that you are using SRC1 to sweep the base current and SRC2 to sweep the collector voltage. A DC bias-current sweep typically involves very small increments – on the order of microamperes, for example. Inside the program, the SRC1 sweep always occurs inside the SRC2 sweep, so the net effect is that the base current is changing more frequently. Because of the small increments in the current sweep, proceeding from one current value to the next may not change the circuit state (operating point) in the simulator. This causes the program to converge to the same solution as the previous current value, resulting in jagged I-V curves.
• Check if you are measuring the DC current in the wrong direction. By default, positive current through a two-terminal element, such as a resistor or ammeter, is measured as flowing from pin 1 to pin 2. To measure current in the opposite direction, you can edit the schematic by changing the element's orientation, or specify the current at a different pin, or change the orientation of the current probe.
• If you are having convergence problems during a swept DC simulation, reduce the step size of the parameter being swept.

Adjusting Tolerance Parameters

Several tolerance parameters can be changed so that simulations are more likely to converge, although at the cost of a somewhat less accurate result. These parameters include:

• Current relative tolerance ( I_RelTol )
• Voltage relative tolerance ( V_RelTol )
• Current absolute tolerance ( I_AbsTol )
• Voltage absolute tolerance ( V_AbsTol )

The equations that are used to check for convergence apply to all analysis types, not just DC. In ADS, you can change these parameters in the Options component on the Convergence tab.

Topology Check and Correction

By default, a topology check is performed before any simulation is executed. The topology check finds common circuit errors that would lead to more serious errors later in the DC simulation. These errors are reported in the Simulation/Synthesis Messages window. See Setting the Topology Checker Mode to learn how to turn the topology checker on and off, and to change the error message format. However, it is recommended to keep the topology checker turned on.

The topology check verifies the existence of the following conditions, some of which are corrected automatically by the simulator if the topology checker is turned on:

• There are no degenerate nodes.
  At least two components must be connected to each node. Degenerate nodes have only one device attached to them, making it difficult for the simulator to solve the circuit. If the topology checker is on, the simulator automatically corrects this problem by inserting a large resistor with a default value of 1e12 ohms from the offending node to ground. The value of the resistor is controlled by the GMIN parameter in the Options component.
• There is a DC path from every node to ground.
  If the DC circuit simulation is to succeed, all circuit nodes must have a DC path to ground. This eliminates nodes that float at an undefined DC voltage value and allows the DC simulator to find the bias point of all nodes in the circuit. This error is commonly caused by two capacitors in series. If the topology checker is on, the simulator corrects this problem automatically by inserting a large resistor with a default value of 1e12 ohms from the offending node to ground. This adds a DC path to ground without affecting the circuit's performance. The value of the resistor is controlled by the GMIN parameter in the Options component.
• There are no devices in series with current sources.
  Devices in series with a current source create problems during DC simulation. This should be corrected manually.
• There are no loops of DC shorts, or voltage or current sources.
  It is possible to create a circuit containing short-circuited DC loops that cannot be handled by the DC simulation. For instance, if two ideal inductors are connected in parallel, they create a DC short-circuit loop. The DC current in this loop is undefined; it can have any value without affecting the circuit solution. This should be corrected manually.
• There are no devices parallel to voltage sources.
  Devices parallel to a voltage source create problems during DC simulation. This should be corrected manually.

The following figures show examples of the topology conditions checked when the topology checker is turned on. The simulator corrects the errors such as those shown in the first figure below by inserting a large resistor (default = 1e12 ohms) from the offending node to ground. However, the simulator cannot correct the errors such as those shown in the second figure, which you should correct manually. Additionally, the topology checker does not check and correct any of these conditions through transmission lines.

By default a summary of the topological problems found is printed to the Simulation/Synthesis Messages window when the topology checker is turned on. To see a list of all the nodes that have topological problems, set the message format mode to verbose.

Common circuit errors corrected during topology check

Common circuit errors not corrected during topology check

If the circuit fails to simulate due to topological problems, turn off the topology checker. This will eliminate all topology checking, and simulations will proceed directly to the DC simulation stage. The DC simulator will speed up simulations slightly, which may be helpful in rare cases where it is certain that the DC simulation will succeed despite the topology.

Note Errors found by the topology checker almost always lead to DC simulation failures, so turning off the topology checker is not recommended.

If you have existing circuits in which there are many topological problems, turning on the topology checker could significantly speed up the simulation. In this case the topology checker corrects the common topological problems before the circuit is simulated.

Setting the Topology Checker Mode

The topology checker parameters are located with the simulator Options. These parameters enable you to turn the topology checker on (default is TopologyCheck=yes ) and turn it off ( TopologyCheck=no ). You can also set the warning messages format to summary (default is TopologyCheckMessages=summary ) or verbose ( TopologyCheckMessages=verbose ).

To change these settings in dialog boxes place an Options component on your schematic, open its setup dialog box, then see the Misc tab. To turn on the topology checker, enable Perform topology check and correction. Disable the setting to turn it off. To set the message format, choose Summary or Verbose for Format topology check warning messages.

Checking Nodes and Pins

If the topology check fails, the offending nodes are highlighted in the Simulation/Synthesis Messages window. Choose Simulate > Highlight Node to identify these nodes.

Unconnected Wire Errors

In the case of a circuit with a wire that is missing, a message such as the following can appear in the Simulation/Synthesis Messages window during a simulation:

Warning detected by HPEESOFSIM during DC analysis "DC1".
Circuit as given has no unique solution.
A virtual resistance of 1 TOhms was added to each node.

In the case of unconnected wires or pins, choose Tools > Check Representation, then select Open connections and click OK. All unconnected wires and components are highlighted, making them easily visible on the screen. Connect these to the correct circuit node.

Port/Pin Mismatches

To check for mismatches between ports and named pins on an underlying schematic, use the Check Representation feature. Choose Tools > Check Representation, then select Port/Pin mismatches and click OK. In a circuit without a topology problem, the simulator reports the following:

Unconnected pins: 0
Port/Pin mismatches: 0

Where a wire is missing between two pins, for example, the components and the disconnected pins will be highlighted in red on the schematic, and a message such as the following will appear, indicating the coordinates of the connectors:

Unconnected pins: 2
I_DC SRC1, pin 2 (2.500,-0.125)
BJT_NPN BJT1, pin 2 (3.250,0.375)

To clear the highlighting, choose View > Clear Highlighting.

Note Always ensure that there is no duplication of port numbers.

Impossible Circuits

A circuit can fail to have a solution. Examples of such impossible circuits are circuits with two DC current sources (or, perhaps, current-mirror circuits) in series. The simulator attempts to analyze these circuits by adding a large resistor in parallel with every node in the circuit. If the DC simulation then succeeds, the resistor value is increased as high as possible (up to 1 Tohm). This allows the DC simulation to proceed, and usually to succeed. However, the offending circuit node or nodes often cause problems with a subsequent harmonic balance simulation because the harmonic balance simulator does not add these resistors. It is best to find the problem node and manually add a DC path (such as a large resistor) to ground.

If virtual resistors were added to each node during DC simulation but the simulation still failed, look for circuit problems such as loops of inductors and voltage sources.

Model Parameter Imax is Too Small

If the RHS_NORM oscillates between/among iterations, the reason could be that the diode's p-n junction in this circuit conducts more than 1 A. The default values of Imax for nonlinear semiconductor devices are around 1 A. It is possible that all device's p-n junction currents in a circuit do not exceed Imax after the circuit converges but have problems converging during the iteration process because of the small Imax. The remedy is to increase nonlinear device model parameter Imax to 1e3. For BSIM3, the model parameter is Ijth.