SP_FET (S-Parameters vs. Bias for FET)

Symbol

Parameters

VGS_start = initial gate-source voltage
VGS_stop = last gate-source voltage
VGS_points = number of gate-source current values
VDS_start = initial drain-source voltage
VDS_stop = last drain-source voltage
VDS_points = number of drain-source voltage values
AnalysisFreq = single S-parameter analysis frequency
Port1Z = port 1 port impedance (complex)
Port2Z = port 2 port impedance (complex)

Notes

1. A template using this item can be accessed by selecting Insert > Template > SP_FET_T from the Schematic window.
2. SP_FET sets up an S-parameter analysis at one frequency with two swept voltage, one each for the for the gate and drain bias. This component helps select an operating point for desired gain. Connect it to a field effect transistor, as indicated in the schematic symbol.
3. This is a simulation component. No other simulation or control components are needed.