# Implementing a Digital Filter

This chapter describes the steps involved in implementing a digital filter design using Digital Filter Designer. It also includes reference and background information on the available options in the three broad implementation areas: structure, scaling, and quantization.

The implementation structure determines the realized structure of a filter, the scaling determines the numeric precision used to represent the coefficients, and the quantization option determines the relative importance of overflow and quantization.

By default Digital Filter Designer generates both ideal and scaled coefficients for a filter that you design. It also offers you the option of disabling the implementation options to speed up the filter design process. You should consider disabling the implementation options when your goal is to generate ideal coefficients only, using the full IEEE double precision or machine-defined standard without any number rounding or saturation.

You can disable the implementation options by choosing **Options** > **Disable/Enable** **Conversion** from the Digital Filter Designer menubar.

The three broad implementation options for a digital filter design using Digital Filter Designer are as follows.

## Choosing an Implementation Structure

Choose the desired structure to implement the digital filter you have designed. Depending upon the filter response type, one or more of the implementation structure options may not be available. The implementation structures are supported for FIR filters while a range of Cascaded second order structures are supported for IIR filters. The implementation structure you choose is used to generate a schematic within Advanced Design System. Implementation only affects the schematic that is generated, and has no effect on the coefficients or the analysis data.

### FIR Filter

To specify the structure for the fixed-point implementation of an FIR filter, choose the desired option from the Implementation Structure list.

#### Direct

The Direct structure is typically used to implement the simplest form of a fixed-point FIR filter. This structure allows highly parallel architecture because all the additions and coefficient multiplications can be done simultaneously. The final addition can be performed either with a single, multiple-input adder or with parallel adders. In this structure, the past *N* input samples are directly accessible from their respective delay blocks.

#### Direct Transpose

In the Direct Transpose structure inputs are multiplied by each filter coefficient before being delayed. As a result multiplications can be avoided in filters that contain duplicate coefficients. For example, the Direct Transpose structure can implement a symmetric, fixed-point FIR filter with half as many multipliers as there are coefficients.

#### Direct Transpose Symmetric

The Direct Transpose Symmetric structure is only available for symmetric FIR filters and it takes advantage of the properties of the Direct Transpose structure.

### IIR Filter

To specify the structure for the fixed-point implementation of an IIR filter, choose the desired option from the Implementation Structure list.

Note Different implementation structures are used to minimize quantization effects that occur as a result of coefficient scaling with the use of a fixed-point numeric format and finite-precision arithmetic. When you use the ideal floating-point numeric format, the schematic generated remains constant for all implementation structures. The following "ideal" structure is used to implement a floating-point design for an IIR filter. |

#### Cascaded 2nd Order

The Cascaded Second Order structure implements a cascaded, fixed-point IIR filter. This structure relates directly to the IIR difference equation.

#### Cascaded 2nd Order Transpose

The Cascaded Second Order Transpose structure reverses the cascaded second order implementation of the poles and zeros in the fixed-point IIR filter.

#### Direct II Cascaded Second Order

The Direct II Cascaded Second Order structure implements a design with the minimum number of delays and multiplications in the fixed-point IIR filter.

#### Direct II Transpose Cascaded Second Order

The Direct II Transpose Cascade Second Order structure reverses the Direct II implementation of the poles and zeros. This is typically done when the IIR filter is implemented on a fixed-point processor or in the presence of noise.

## Selecting the Numeric Format

Select the numeric format based upon the purpose, and resources available for the implementation, of a filter design. Any change in the numeric format causes the filter response to deviate from the ideal.

Keep in mind that any change in the numeric format or bit width affects the performance of the filter. Be sure to check that the filter performance is acceptable after any changes to these specifications. Within Digital Filter Designer, an ideal filter analysis is always presented to enable you to compare the deviation between what is theoretically possible and what is physically realized, based upon your implementation criteria. This ideal analysis is based upon the full IEEE double precision or machine-standard definition.

In a schematic generated for a scaled filter design, you can use the global parameters component (VarEqn) to change design parameters and propagate the change across the entire design rather than manually editing the parameters for each component.

Hint If your goal is to generate ideal coefficients only (using the full IEEE double precision or machine-defined standard without any number rounding or saturation), you can disable the implementation or conversion options by choosing Options > Disable/Enable Conversion from the Digital Filter Designer menubar. |

When the floating-point format option is selected, it scales to the IEEE single precision definition to achieve a word length of 23 with a fractional length of 8.

The fixed-point format with a bitwidth of *n* uses 1 bit to represent the sign bit and *n-1* bits to represent the fractional coefficients.

To select an numeric format, click the desired format option.

Note A scaled floating-point or single precision schematic can't be generated if the simulator does not provide the library support for the required components. |

### Specifying the Bit Width

Specify the coefficient precision or bit width when implementing a filter design using the fixed-point numeric format. Keep in mind that a fixed-point format with a bitwidth of *n* uses 1 bit to represent the sign bit and *n-1* bits to represent the fractional coefficients.

To modify the bit width, replace the existing value with the desired value in the Bitwidth field.

## Selecting the Norm

Select a norm based upon the quantization criterion you wish to emphasize in the implementation of the filter design.

To select the norm, click the desired option.

### L Infinity

Use this option to prevent overflow at the expense of high quantization noise. This option scales the coefficients so that the maximum magnitude response (for each section in the IIR case) is unity.

### Fractional

Use this option when no scaling is desired. With this option, only when a coefficient is greater than unity it is scaled just enough to make its largest value fractional.

### L 1

Use this option to achieve a reasonable compromise while trying to minimize both overflow error and quantization noise. This option scales the coefficients so that the sum of their absolute values is one.

Note An IIR filter may exhibit larger attenuation from unity after scaling. This is especially true for IIR filters that have poles close to the unit circle. Digital Filter Designer attempts to alleviate this effect by implementing the filter sections containing the poles closest to the unit circle at the edge closer to the filter output. |

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