1-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power Contours at X dB Gain Compression

Description

This simulates the output power and power-added efficiency contours of a device or amplifier at a single RF frequency at the X dB power gain compression point, as a function of the load reflection coefficient, at the fundamental frequency. You can specify the amount of gain compression, X, in dB. The simulator then increases the available source power to the device until the power gain has been reduced by X dB, relative to its small-signal value. A sample device is provided. You must replace this device with your own device or amplifier, and modify the biases, as needed.

Needed to Use Schematic

A device or an amplifier using nonlinear model(s)

Main Schematic Settings

Input frequency and power, circular region of the Smith chart, specifying load reflection coefficients, load impedances at harmonic frequencies (Z_l_2 - Z_l_5), and source impedances at the fundamental and harmonic frequencies (Z_s_fund - Z_s_5.)

Data Display Outputs

All at the X dB gain compression point:

• Contours of equal power-added efficiency and power delivered, on a Smith chart
• Maximum power-added efficiency, in percent and maximum power delivered in dBm
• Contours of equal power-added efficiency and power delivered, on a Smith chart renormalized to an arbitrary impedance
• Contours of equal power-added efficiency and power delivered, on a rectangular plot
• The simulated load impedances on a Smith chart, and the PAE, power delivered, and the impedance corresponding to a marker location

Schematic Name

HB1Tone_LoadPull_GComp

Data Display Name

HB1Tone_LoadPull_GComp.dds

Notes

1. You can delete one of the two supplies and/or replace the voltage sources with current sources, and the PAE calculation will still be valid. You can modify the components in the bias network, realizing that the DC power consumption is computed as (the DC voltage at the Vs_high node) * (the DC current in the Is_high current probe) + (the DC voltage at the Vs_low node) * (the DC current in the Is_low current probe).
2. For some load impedances, the device might be unstable. For this reason, you might want to simulate the stability circles of the device at a particular bias point, to check for instabilities. To do this, copy the biased device into the schematic generated from the menu selection DesignGuide > Amplifier > S-Parameter Simulations > S-Params., Noise Fig., Gain, Stability, Circles, and Group Delay. The stability circles are on one of the data display pages that will be updated after you run a simulation using this schematic. Avoid using load impedances within the unstable region if the load stability circle is inside the Smith chart. You might also want to use some of the other DesignGuide schematics to test for stability with a large input signal.