2-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power, IMD Contours

Description

This simulates the output power, power-added efficiency, and 3rd- and 5th-order intermodulation distortion contours of a device or amplifier with two input tones at one power level, as a function of the load reflection coefficient, at the fundamental frequency. A sample device is provided. You must replace this device with your own device or amplifier, and modify the biases, as needed.

Needed to Use Schematic

A device or an amplifier using nonlinear model(s)

Main Schematic Settings

Center frequency of the two input tones, the frequency spacing between them, available source power (from both tones), maximum order of the intermodulation terms to be computed, and the bias settings. The load reflection coefficients are specified by defining a circular region of the Smith chart. Load impedances at harmonic frequencies (Z_l_2 - Z_l_5), and source impedances at the fundamental and harmonic frequencies (Z_s_fund - Z_s_5) can also be specified.

Data Display Outputs

• Contours of equal power-added efficiency and power delivered, on a Smith chart
• Maximum power-added efficiency, in percent and maximum power delivered in dBm
• Contours of equal power-added efficiency and power delivered, on a Smith chart renormalized to an arbitrary impedance
• Contours of equal power-added efficiency and power delivered, on a rectangular plot
• Contours of equal 3rd- and 5th-order intermodulation distortion (IMD), on a Smith chart
• Minimum 3rd- and 5th-order IMD, in dBc
• Contours of equal 3rd- and 5th-order IMD, on a Smith chart renormalized to an arbitrary impedance
• Contours of equal 3rd- and 5th-order IMD, on a rectangular plot
• The simulated load impedances on a Smith chart, and the PAE, power delivered, 3rd- and 5th-order intermodulation distortion and the impedance corresponding to a marker location

Schematic Name

HB2Tone_LoadPull

Data Display Name

HB2Tone_LoadPull.dds

Notes

1. You can delete one of the two supplies and/or replace the voltage sources with current sources, and the PAE calculation will still be valid. You can modify the components in the bias network, realizing that the DC power consumption is computed as (the DC voltage at the Vs_high node) * (the DC current in the Is_high current probe) + (the DC voltage at the Vs_low node) * (the DC current in the Is_low current probe).
2. For some load impedances, the device might be unstable. For this reason, you might want to simulate the stability circles of the device at a particular bias point, to check for instabilities. To do this, copy the biased device into the schematic generated from the menu selection DesignGuide > Amplifier > S-Parameter Simulations > S-Params., Noise Fig., Gain, Stability, Circles, and Group Delay. The stability circles are on one of the data display pages that will be updated after you run a simulation using this schematic. Avoid using load impedances within the unstable region if the load stability circle is inside the Smith chart. You might also want to use some of the other DesignGuide schematics to test for stability with a large input signal.