DC and Bias Point Simulations > FET I-V Curves, Class A Power, Eff., Load, Gm vs. Bias

Description

This simulation setup generates the I-V curves of a FET. Various data dependent on the I-V curves, such as transconductance, class A output power, and efficiency are also shown. Both the gate and drain voltages are swept.

Needed to Use Schematic

Nonlinear FET model

Main Schematic Settings

Sweep ranges for gate and drain voltages

Data Display Outputs

FET_IV_Gm_PowerCalcs.dds, "ClassA_calcs" page:

• Device I-V curves
• Load line set by placing a marker on the I-V curves at the knee, and by a user-specifiable maximum VDS
• Maximum allowed DC power dissipation curve, with maximum dissipation set by user.
• Given the load line specified by the knee of the I-V curves and the maximum VDS:
  • Optimum drain voltage and drain current, for maximum power delivered to the load while in Class A operation
  • Corresponding load resistance
  • Corresponding maximum output power
  • Corresponding DC power consumption
  • Corresponding DC-to-RF efficiency
• Given a different bias point, specified by a different marker:
  • Load line between that marker and the marker at the knee of the I-V curve
  • Resistance of this load line
  • DC power consumption at this bias point
  • Output power, assuming the device remains in Class A operation (AC voltage does not exceed user-specified VDS, and does not enter the knee region)
  • DC-to-RF efficiency at this bias point

Note The estimates of DC-to-RF efficiency and output power are only approximate, since no high-frequency effects are modeled in this simulation.

FET_IV_Gm_PowerCalcs.dds, "IV, Gm vs. Bias" page:

• Device I-V curves
• DC transconductance (Gm) versus VDS
• DC transconductance (Gm) versus VGS and VDS
• DC transconductance (Gm) versus drain current
• Drain current versus gate voltage at one VDS
• Table of transconductance values

Schematic Name

FET_IV_Gm_PowerCalcs

Data Display Name

FET_IV_Gm_PowerCalcs.dds