DC and Bias Point Simulations > FET Output Power, Distortion vs. Load R

Description

This simulation setup generates the I-V curves of a FET and simulates the power delivered to a load resistor as a function of the resistance value, at one bias point.

Needed to Use Schematic

Nonlinear FET model

Main Schematic Settings

Sweep ranges for gate voltage, drain voltage and load resistance; bias point and frequency for output power versus load resistance simulation

Data Display Outputs

• Device I-V curves
• Load lines for each of the load resistances
• Power delivered to the load as a function of load resistance
• Output power and harmonic distortion at each load resistance

Schematic Name

FET_dynamic_LL

Data Display Name

FET_dynamic_LL.dds

Note

The load power simulations are going to show less than optimal results as the simulation frequency is increased, because only a resistive load is presented to the device. Also, no impedance matching is included at the input.