PLL QuickStart Guide

This PLL QuickStart Guide is intended to help you get started using the Phase-Locked Loop Design Guide effectively. For detailed reference information, refer to PLL DesignGuide Reference.

Note This document is written describing and showing access through the cascading menu preference. If you are running the program through the selection dialog box method, the appearance and interface will be slightly different.

The PLL DesignGuide has many simulation setups and data displays that are very useful for designing a phase-locked loop. The simulation set-ups are categorized by the PLL configuration, simulation technique, and type of phase detector and low-pass filter. The simulation set-ups are for analysis.

Note This DesignGuide is not a complete solution for all phase-locked loop techniques, but covers the most common approaches. Subsequent releases of this DesignGuide will include an expanded range of features.

Using DesignGuides

All DesignGuides can be accessed in the Schematic window through either cascading menus or dialog boxes. You can configure your preferred method in the Advanced Design System Main window. Select the DesignGuide menu.

The commands in this menu are as follows:
DesignGuide Studio Documentation > Developer Studio Documentation is only available on this menu if you have installed the DesignGuide Developer Studio. It brings up the DesignGuide Developer Studio documentation. Another way to access the Developer Studio documentation is by selecting Help > Topics and Index > DesignGuides > DesignGuide Developer Studio (from any ADS program window).
DesignGuide Developer Studio > Start DesignGuide Studio is only available on this menu if you have installed the DesignGuide Developer Studio. It launches the initial Developer Studio dialog box.
Add DesignGuide brings up a directory browser in which you can add a DesignGuide to your installation. This is primarily intended for use with DesignGuides that are custom-built through the Developer Studio.
List/Remove DesignGuide brings up a list of your installed DesignGuides. Select any that you would like to uninstall and choose the Remove button.
Preferences brings up a dialog box that allows you to:

• Disable the DesignGuide menu commands (all except Preferences) in the Main window by unchecking this box. In the Schematic and Layout windows, the complete DesignGuide menu and all of its commands will be removed if this box is unchecked.
• Select your preferred interface method (cascading menus vs. dialog boxes).
  

Close and restart the program for your preference changes to take effect.

Note On PC systems, Windows resource issues might limit the use of cascading menus. When multiple windows are open, your system could become destabilized. Thus the dialog box menu style might be best for these situations.

Basic Procedures

The features and content of the PLL DesignGuide are accessible from the DesignGuide menu found in the ADS Schematic window.
To access the documentation for the DesignGuide, select either of the following:

• DesignGuide > PLL > PLL DesignGuide Documentation (from ADS Schematic window)
• Help > Topics and Index > DesignGuides > PLL (from any ADS program window)

You have the option of selecting a PLL Configuration or choosing to examine one of the various RFIC PLL examples. The RFIC examples are subsets of the various PLL configurations, whereby device level components replace the phase detector and prescalar model components.

Using a dialog box of Phase-Locked Loop schematics, you select your desired PLL configuration, as shown here.

You select one of the available PLL configurations shown.
Having identified the type of PLL structure, you then select one of the three simulations available from the Simulation tab, as shown here. The simulations include

• Closed and Open Loop frequency response
• Phase Noise response
• Transient response
  

You then need to identify the phase detector and low-pass filter used in your design. Some combinations are unavailable at this time but are expected to be available in future upgrades.
The selection box for phase detectors is shown here.

Shown here is the selection box for loop filters. The grayed-out selections are not available at this time. Right-click one of the available selections. For a detailed description of the loop filter selections, refer to the PLL DesignGuide Reference.

Selecting Appropriate Configurations

The Phase-Locked Loop DesignGuide is broken up into different sub-categories, as shown in the previous section. The specifications that you select depend on your desired simulation and the type of PLL structure that your system can utilize.

If, for example, you are designing a synthesizer, you can start with the loop frequency response configurations shown in the section Phase Margin and Unity Gain Bandwidth. The output parameters will be used for evaluating the phase noise and transient responses.

Most of the information on the data display for this design simulation and others is in a format that engineers can easily understand. The visibility of equation syntaxes is minimized. Information about items on a data display that you will want to modify is enclosed in red boxes.

Phase Margin and Unity Gain Bandwidth

The optimization procedure based on achieving a desired Phase margin and Unity Gain Bandwidth is shown here. Enter your desired values, as well as your VCO tuning parameter, the divide ratio, and the Phase Detector characteristics. (Enter this data in the area of the schematic encircled in the following illustration.)

In the data display results shown here, the resultant Phase Margin and Unity Gain Frequency are displayed, along with the optimized loop filter parameters. If the objectives have not been met, you should adjust the loop filter parameters to alter the initial conditions of the optimization and re-run the simulation.

Phase Noise Response

The parameters derived from the Loop Frequency Response schematic should be entered into the Phase Noise Response schematic.

The phase noise characteristics of each component should be set on each subcircuit block. The F and L parameters that describe the noise versus frequency characteristics are depicted in the schematic.
The data display corresponding to the Phase Noise schematic is shown here.

The graph on the left displays the individual noise source's contributions and the graph on the right shows the overall noise performance of the PLL.

Transient Time Response

Shown here is the schematic for evaluating the transient time response of a synthesizer.

The loop filter parameters derived from the Loop Frequency response need to be entered into this schematic, along with the VCO and Phase Detector constants. The transient response requires additional parameters such as the Reference Frequency and the stop and delay time, as well as the Divider Ratio step change.

The Transient response data display has several figures that will describe the PLL performance as a function of time. From this display, you can evaluate the settling time and use the results to debug the phase-locked loop.