80211a Practical Systems

Receiver Test Benches

802.11a Receiver Specifications- Sensitivity

Defined as the minimum RF signal level required to achieve a Packet Error Rate (PER) <10% at PSDU length of 1,000 bytes.

802.11a Receiver Specifications-Adjacent Channel Rejection

The desired signal strength is set at 3dB above the rate-dependent sensitivity, the interfering signal is raised until 10% PER is reached for a PSDU length of 1,000 bytes. The power difference between the interfering signal and the desired signal is the adjacent channel rejection.

Note Due to the increased bandwidth required by adjacent and alternate channel simulations, it is necessary to decrease the simulation time step by a factor of 2 to 4 times, and to increase the order of the IFFT/FFT from 6 to 8 or 9. The simulation time will correspondingly increase with these changes. Also, at this time data displays and datasets may not be provided for some alternate channel test benches.

802.11a Receiver Specifications-Alternate Channel Rejection

The desired signal strength is set at 3dB above the rate-dependent sensitivity; the interfering signal is raised until 10% PER is reached for a PSDU length of 1000 bytes. The power difference between the interfering signal and the desired signal is the adjacent channel rejection.

Zero-IF Receiver Test Benches

The Zero-IF receiver topology is desirable for use in 802.11a systems for various reasons of cost, complexity and performance. However, it is prone to generating dc offsets due to Local Oscillator (LO) leakage. Also, an automatic gain control (AGC) capability is required in any receiver implementation. The WLAN DesignGuide provides a test bench to investigate these effects.

Receiver Dynamic Range, CCA and AGC Test Bench

Test bench name: Test_AGCSettling_WLAN_80211a
Specification reference: Section 17.3.10.4, Section 17.3.3, Section 17.3.10.5

The 802.11a modulation requires a linear transmitter and receiver chain. This linearity requirement creates a difficult challenge for the receiver design. Typically, an automatic gain control (AGC) is used in the receiver to ensure that the linearity requirements are met. This model includes a fast, digital AGC that settles within ~5 µ. From the 802.11a standard (Section 17.3.3), the receiver design has 8 µ to perform a signal detection, settle AGC, select diversity (if any), run coarse freq offset adjust and timing recovery.

In this model, AGC runs on the first 5-6 short symbols of the preamble, which produce a fairly constant envelope waveform. The variable AGC settling time (in µ) defines how long AGC runs. Selection of this value is a tradeoff between the dynamic range of the receiver (the dynamic range required of the AGC), AGC step size and step timing, and the aforementioned functions that also need to run in the 8 µ of 10 short symbols.

The top-level model includes a transmitter block, a path loss block, and a receiver block. To run quick simulations to observe various points in the receiver and AGC sections, enable the TKShowValues and TKPlots to observe real-time effects. For more detailed analyses, disable these blocks and enable the TimedSinks at the various points on the top-level model. The major points of interest include: Filtered_AGCDetout, RSSI_CCA_Indicator, ReceiverEVM, and AGC_Value. A data display is set up, Test_AGCSettling_WLAN_80211a, which includes the outputs of many of these time sinks. If you are interested in the performance of AGC vs. the entire RX dynamic range, enable the ParameterSweep for PathLoss and this will sweep the input signal to the receiver from -4 to -64 dBm.

Following are the variables used in the simulation

The data display shows many key parameters of the 8021.11a receiver. One of the most critical items is in this design is AGC settling time vs. EVM or BER/PER. The data display shows plots of AGC vs. time, RSSI (received signal strength indicator) vs. time, EVM vs. time and other important design considerations.

The receiver (push into RECEIVER_ZIF_AGC) used in this model includes a RX Frontend component (RF filter, T/R Switch, and LNA), a DEM QAM mixer, a pair of linear baseband amplifiers (BB1), followed by an AGC block, with the last blocks being a pair of nonlinear baseband amplifiers (BB2). The typical parameters for each stage are defined at the top-level model: LNAGAIN, LNANF, BB2Gain, etc. For this model it was assumed that the non-linear effects of all stages prior to BB2 could be ignored.

OFDM systems such as 802.11 have a large >10 dB peak-to-average signal value. This requires a backoff from P1dB for BB2 to keep this stage from compressing. This backoff is determined by the variable Det0P1dB on the top-level model. This variable defines the output signal level of BB2 that the AGC attempts to maintain. For example, if Det0P1dB=17 dBm, the digital AGC will try to keep the output of BB2 to +17dBm. Consequently, the backoff is determined by BB2 P1dB - Det0P1dB.

As previously mentioned, the digital AGC always tries to keep the output envelope of the BB2 pair at a constant level. It does this by first calculating the signal amplitude, at BB2 output, by the math function SQRT(I ² +Q ² ). This level is then compared with 5 detector levels that control 4 different AGC states: -5 dB, -1 dB, +1 dB, and +5 dB. The digital AGC works by comparing the input signal amplitude with 5 threshold values and applying an appropriate gain adjustment to attempt to keep the BB2 output constant. For example, if the input signal is greater than the defined AGC trip point (Det0P1dB) by >5 dB, then the threshold for the -5 dB AGC is triggered, this results in a 5 dB increase in attenuation for that AGC time step. A similar comparison is made for the next time step. Eventually, if the signal is within the dynamic range of the receiver, AGC should converge between the +1 and -1 dB AGC trip points, when this occurs no more AGC is applied. Similarly, if the signal is too small or AGC overshoots its defined value, attenuation can be taken out with the +1 and +5 dB stages. Due to its complexity, the AGC is not shown here, but you can push into AGC0v3B to view it after loading the design.

The AGC model uses a few parameters that are important to note. The AGC time step is defined by the clock that feeds the 5 CounterSyn blocks. AGC can make a step every 0.167 µ. AGC is disabled or frozen by toggling Port 8 which disables the AGC step clock. The current AGC model has 96 dB of dynamic range defined by the two constant blocks set to 0 and -96 dB. There are several ports available to monitor real-time AGC functions in this model such as detector output.

This model also calculates RSSI/CCA with the blocks in the top-level. These take the measured detector value at the output of BB2, subtract all linear gains of all receiver blocks, and add the AGC value to calculate an input referred power.

Specification reference: IEEE802.11a-1999 Sections 17.10.2 and 17.10.3

IEEE802.11a section 17.3.10.2 specifies adjacent channel rejection requirements; section 17.3.10.3 specifies alternate channel rejection requirements.

Adjacent channel centers in IEEE 802.11a are offset from the desired channel center by 20 MHz; alternate channels are offset by 40 MHz.

In this example, the data rate is 48 MHz. To perform adjacent channel rejection testing at this data rate, the specification requires the desired channel power input to the receiver be -63 dBm. An adjacent channel also applied at -63 dBm must not cause the packet error rate (PER) to exceed 10%. To perform alternate channel rejection testing at this data rate, the desired channel power input to the receiver is -63 dBm. An alternate channel applied at -47 dBm must not cause the PER to exceed 10%.

WLAN library components are used to generate the short preamble, the long preamble, the signal field and the data of the 802.11a transmit signal. The final module in the 802.11a signal generator is the sub_RF_Mod_OFDM block. Transmit filtering is applied at baseband in the sub_RF_Mod_OFDM module and the IQ baseband signal is mixed to the RF frequency specified by the Fcarrier variable. The power level output from the signal generator is set in dBm by the SignalPower variable.

Two options for generating the interferer signal are provided.

• The interferer is produced by delaying and amplifying a copy of the desired channel signal. This technique runs more quickly, but results may be affected by correlation between the interferer and desired channels.
  
• A separate 802.11a signal generator is used to produce the interfering signal. To ensure that the desired and interfering channels are uncorrelated, the interferer generator uses a different data set and OFDM packet length than the desired channel. The packet length of the desired signal is set by the Length variable. The packet length of the interferer is set by the "Length2" variable. Using this interferer generation technique, simulations with BlockNum equal to 30 required about 3 times more time to run the same simulations using delayed desired signal as the interferer.

Both options use the Interferer_dB level variable to set the signal level of the interferer in dB relative to the desired signal and the InterfererOffset variable to set the frequency offset of the interfering channel from the desired channel in MHz.

The interferer and desired channel signals are combined and input to the Zero IF Receiver block. The RF section of the ZIF receiver represents the loss and gain of filters, matching circuits, and RF amplifiers. Following the receiver RF stage, the desired signal is mixed down to baseband IQ signals. Baseband filters provide rejection of the interfering adjacent or alternate channel signals. The automatic gain correction of the ZIF receiver is disabled, and fixed gain blocks are installed to replace it. This simplification reduces simulation time and should not affect adjacent or alternate channel rejection. The output of the ZIF receiver goes to amplifier block G6. The signal level required by the demodulation modules of the receiver is a function of the Order variable. Gain block G6 provides this required signal level adjustment.

WLAN library components demodulate the baseband IQ signal into digital data. The WLAN_BERPER module compares the demodulated signal data output to the data input to the signal generator. The BER and PER are then calculated and output to data sinks.

The display provides plots of the RF signal spectrum at the input the ZIF receiver input. The spectrum at the filter input and the output on one receiver baseband signal path is also plotted. A plot also shows the BER and PER values as PPDU frames are received.