Writing Design Rules

This chapter provides information for writing design rules. Design verification rules produce this information:

• Graphical data showing the location of each violation.
• An error message showing the nature of the violation.

A complete DRC example is included in this section. For detailed information on specific commands, see the command reference chapters.

Extension and Intrusion Definitions

The terms, Extension and Intrusion, used in creating design rules, are defined in the following illustration.

Anatomy of a Simple DRC Rule File

A DRC rule file is written in Application Extension Language (AEL). The illustration shows a simple DRC rule file. Typically, a rule file consists of a Layer section and a Rule section. The Layer section declares all the design layers used or checked and all the output DRC layers for displaying errors. The Rule section consists of rule checking statements.

Note A comment starts with a // or is enclosed by /* and */ .

Layer Management

The rules file illustrated in this section analyzes data on the physical design layer cond. The width command checks the inside clearance distance between edges of the same polygon. Edges that are less than 3.0 layout units apart are exported as line segments to design layer error101. Each violation has an associated error message: width less than 3.0.

The AEL variable lyrCond references an import layer and the AEL variable lyrError101 references an export layer.

Import Layers

When performing a design rule check, you must specify the design layers you want checked for design violations. Design layers from your layout design are imported into the verification process using the command dve_import_layer .

You can specify an import layer by using a layer name or a layer number:

decl lyrCond = dve_import_layer ("cond");

or

decl lyrCond = dve_import_layer (1);

Import layers can be used only as input to a DRC command. An import layer must be an existing Physical design layer and can only be used for import (that is, it cannot appear again on the left-hand side of a rule command).

Export Layers

Data is exported back to the layout editor by sending the output of the dve_drc command to an export layer. You create export layers using the command dve_export_layer .

You can specify an export layer by using a layer name or a layer number:

decl lyrError101 = dve_export_layer ( " error101 " );

or

decl lyrError101 = dve_export_layer (101);

An export layer must be an existing DRC design layer. The Design Rule Checker will not display DRC errors on a Physical layer.

When sending a DRC error to an export layer, the += assignment is used to signify that you are performing an append operation. Export layers are always empty at the beginning of each DRC invocation, so it is safe to use the += append assignment when sending data to an export layer.

Export layers cannot be used as input to a DRC command. Export layers can appear only on the left-hand side of a rule command.

Work Layers

Work layers are used to reference intermediate data generated by a rule command. Work layers exist only temporarily while the DRC process is running, and are not part of the layout editor environment.

Use work layers when it is necessary to filter or process data on an import layer before generating a DRC error.

As good practice, you should always initialize a work layer to NULL .

Rules File Layers Example

This rules file example analyzes physical design data on layers cond and cond2. New polygons are created that represent the area where polygons on layer cond overlap polygons on layer cond2. The new polygons are placed in a work layer lyrPolyOverlap.

The all_edges command identifies the entire polygon as an error and the data is exported to DRC layer error101.

decl lyrCond = dve_import_layer ("cond");
decl lyrCond2 = dve_import_layer ("cond2");
decl lyrError101 = dve_export_layer ("error101");
decl lyrPolyOverlap = NULL;
lyrPolyOverlap = dve_bool_and (lyrCond, lyrCond2);
lyrError101 += dve_drc (all_edges (lyrPolyOverlap), "Conductive metal cond overlaps cond2");

Complete DRC Example

The example in this section illustrates writing design rules for Substrate Vias and NiCr Thin Film Resistors and manufacturing rules for Gate Metal. The example covers most of the functionalities and features of the DRC commands.

Note The DRC file used in this example is included in the drc_via_prj directory of the program's examples directory. For information on accessing the examples directory, see Viewing DRC Examples.

To set up a DRC check, you must define the design layers and the error layers. For information on setting up a DRC, refer to Defining the Design Layers and Defining the Error Layers.

The following table shows the layer definitions for the process used in this example.

Defining the Design Layers

The rule section declares these imported design layers:

//  declare input design layers
decl nImplant = dve_import_layer(2);
decl dImplant = dve_import_layer(1);
decl niCr = dve_import_layer(3);
decl ohmic = dve_import_layer(5);
decl isoImplant = dve_import_layer(6);
decl gateMetal = dve_import_layer(7);
decl metal0 = dve_import_layer(9);
decl mIM = dve_import_layer(23);
decl via1 = dve_import_layer(14);
decl metal1 = dve_import_layer(15);}} 
decl airBridgePost = dve_import_layer(10);
decl airBridge = dve_import_layer(11);
decl passVia = dve_import_layer(12);
decl backVia = dve_import_layer(20);
decl backViaCoat = dve_import_layer(21);

Although every layer is declared here, you do not need to declare a design layer if you will not be checking it. This example does not use all of these layers, because you are not checking the complete design.

Defining the Error Layers

After defining the design layers, declare three DRC error layers to display errors from a set of rules. When writing DRC rules, you decide how many DRC error layers are needed to best view the results of a check.

// declare some DRC error layers
decl viaError = dve_export_layer(107); // for substrate via design rule
decl niCrError = dve_export_layer(103); // for thin film resistor rule
decl gateMetalError = dve_export_layer(120); // for gate metal rule

Note DRC error message strings: ( ) and _ are supported, but ` ' are not supported.

Checking the Clearance Rules

DRC checks clearance rules by selecting the edges that violate the clearance constraints and sending these to a DRC error layer. Clearance rules can be checked from either inside or outside of an edge to another edge of polygons.
The types of clearance rules are:

• width

• spacing

• external

• contains

• nests

• internal

Of these, the simplest rule is width.

width

The width command is used to check the width of polygons on a given layer. The command checks the distance from the inside of one edge to the inside of another edge of the same polygon.

Width rules for the substrate via are written as follows:

// Rule A: substrate via feature minimum 30 um

viaError += dve_drc(width(backVia) < 30, "Substrate via feature size < 30");

// Rule B: Substrate Via target size minimum 120 um

viaError += dve_drc(width(gateMetal) < 120, "Substrate via Target size < 120");

spacing

The spacing command is used to check spacing constraints on a given layer. The command checks the distance from the outside of an edge to the outside of another edge.

//
// Substrate Via Spacing Design Rule
// Rule C - Substrate Via to Via minimum spacing 150 um
//

viaError += dve_drc(spacing(backVia) < 150, "Substrate via edge to via edge min. is 150 um");

Two other simple spacing rule commands are notch and gap. The notch command checks the spacing within the same polygon and the gap command checks the spacing between two different polygons. The spacing command checks both cases.

Checking Clearance Between Layers

All the clearance commands mentioned to this point work only on polygons that are on the same layer. Next you will see clearance commands that check the clearance from one layer to another. The layers checked can be a design or work layer, so you can send a design layer to a work layer and perform a two-layer rule command with the original design layer. An example of this capability is shown in the Using Rule Conjunction.

external

The external command checks the external spacing between polygons on two different layers.

//
// Rule D - Substrate Via to Iso. Implant minimum spacing 90 um
//

viaError += dve_drc(external(backVia, isoImplant) < 90, "Substrate via edge to Iso. Implant Edge min. is 90 um");

contains

The contains command is used to check the inclusion of one polygon within another polygon. The command checks the distance from the inside edge of polygons on the first layer to the outside edge of polygons on the second layer.

//
// Rule E - Metal 0 Inclusion in Gate Metal min is 1 um

gateMetalError += dve_drc(contains(gateMetal, metal0) < 90, "Metal 0 Inclusion in Gate Metal min is 1 um");

You can use the contains command to check the extension of one polygon outside another polygon on a different layer. The illustration uses this design rule on NiCr Thin Film Resistors.

// Rule F - Metal 0 Extension from NiCr  min is 0.5 um
//
niCrError += dve_drc(contains(metal0, niCr) < 0.5, "Metal 0 Extension from NiCr  min is 0.5 um", DVE_RN_EDGE_ANGLES, DVE_RV_PARALLEL);

nests

The nests command checks the distance from the outside edge of polygons on the first layer to the inside edge of polygons on the second layer. It is exactly the same command as the contains command except the two layer arguments are switched.

The example writes the previous extension rule (Rule F) using the nests command.

// Rule F - Metal 0 Extension from NiCr  min is 0.5 um
//
niCrError += dve_drc(nests(niCr, metal0) < 0.5, "Metal 0 Extension from NiCr  min is 0.5 um", DVE_RN_EDGE_ANGLES, DVE_RV_PARALLEL);

Notice that a qualifier was used in Rule F. A qualifier is defined as a name-and-value-pair:

Qualifier_Name, Qualifier_Value

Clearance Rule Qualifiers filter in (or out) tests between pairs of edges for a rule step. If no qualifier is specified, a rule command normally checks all the edge pairs. However, in this example, we are interested only in the edge pairs that are parallel to each other. Without the Parallel qualifier, we would get an unpleasant surprise from errors caused by non-parallel edges as shown in the following figure. Remember, contains checks from outside of the first polygon (on NiCr) to the inside of the second polygon (on Metal 0).

A width command appears to work well without a qualifier. What happens to the adjacent edges? Actually, the width command has a default qualifier to filter out all the adjacent edges during the rule operation:

DVE_RN_SEPARATE, DVE_RV_SEPARATE

Nearly all clearance commands have some type of default qualifiers to tell how the rule works. An example would be the Polarity qualifier. The fact that a command checks from the inside (or outside) of an edge to the inside (or outside) of another edge is dictated by the Polarity qualifier.

Two generic clearance commands (single_clearance and double_clearance) demand a polarity qualifier to tell them what to check. The single_clearance command is equivalent to a width command:

dve_drc(single_clearance(layer) < distance,
        DVE_RN_POLARITY, DVE_RV_INSIDE);

The double_clearance command is equivalent to a contains command:

dve_drc(double_clearance(layer1, layer2) < distance,
        DVE_RN_POLARITY_FROM, DVE_RV_INSIDE,
        DVE_RN_POLARITY_TO, DVE_RV_OUTSIDE);

internal

This internal command checks the distance from the inside edge of one polygon to the inside edge of another polygon. The command is used to check the intrusion from one polygon into another polygon.

// 
// NiCr Thin Film Design Rules
// Rule G - NiCr  Intrusion into Metal0  min is 2.5 um
//

niCrError += dve_drc(internal(niCr, metal0) < 2.5, "NiCr  Intrusion into Metal0  min is 2.5 um");

Selecting Polygons

Several polygon selection commands are provided. In this example, only the poly_path_length and poly_inter_layer commands are described, but all polygon selection commands work similarly. For more details, see Conditional Selection.

poly_path_length

The command poly_path_length selects polygons based on the path length property of overlapping polygons on two layers.

To check the width of a Thin Film Resistor, first do a boolean merge-NOT between the NiCr and Metal 0 layers to produce the resistor polygons. The path consisting of Bottom Inside Top (BIT) edges is the width of the resistor (see the illustration). Then select the bad resistors by checking the Bottom Inside Top (BIT) path length.

For details on determining the path code from merged polygons, refer to Polygon Selection Based on Merge Properties.

In this rule example, you begin to use work layers. Also, the result of a poly_path_length command is a polygon layer, so you need an all_edges command to send the polygon layer to a DRC error layer for displaying.

// declare some work layers

decl lyrResistor, widthShort;

//
// NiCr Thin Film Design Rules
// Rule H - Resistor width min is 2um
//
// To produce the resistor polygons
lyrResistor = dve_bool_not(niCr, metal0);

// Select if the BIT path length is less than 2
widthShort = dve_drc(poly_path_length(lyrResistor) < 2, 
        DVE_RN_PATH_CODE, DVE_RV_BIT,    // set path code
        DVE_RN_PATH_LENGTH, DVE_RV_MIN_PATH  // check minimum
);

// Attach error  message  & send error polygons to DRC error layer
niCrError += dve_drc(all_edges(widthShort),
        "NiCr Thin Film Resistor min width 2.0 um"
);

The Rule K checks the length dimension of a resistor. It does not require a poly_path_length command, you can implement this rule by using a boolean command and a clearance command. Try this as an exercise.

poly_inter_layer

The command poly_inter_layer selects a polygon based on its relationship to another polygon. The command is very useful for selecting a subset of polygons out of a polygon layer and then performing a rule check on the subset.

Go back to rule E , which was done previously without filtering out unwanted polygons before applying the clearance command. This rule catches many errors that occur outside of substrate vias because both the Metal 0 and Gate Metal layers are used in the construction of other devices (such as DFET). The clearance rule brings in all of the polygons from these two layers, including the polygons used for DFET.

Fortunately, you can tell when a Metal 0 or a Gate Metal polygon is used for a substrate via: it must enclose a polygon from the Backside Via layer (layer 20), as shown on the illustration. The poly_inter_layer command is used to select polygons like this. Here is the rewritten Rule E:

//
// Substrate Via Spacing Design Rules
// Rule E - Metal 0 Inclusion in Gate Metal min is 1 um
//

// declare some work layers

decl viaGateMetal,viaMetal0; // these are work layers,
                             // that do not map to a real 
                             // process layer
//
// First, derive gate metal used for substrate vias by using
// only the gate metal that encloses the backside via layer
//
viaGateMetal = dve_drc(poly_inter_layer(gateMetal, backVia),
        DVE_RN_INTER_CODE, DVE_RV_ENCLOSE_ONLY);
// 
// In a similar way, derive the metal0 used for substrate vias 
//
viaMetal0 = dve_drc(poly_inter_layer(metal0, backVia),
        DVE_RN_INTER_CODE, DVE_RV_ENCLOSE_ONLY);
//
//  Use contains cmnd to check Inclusion between 2 work layers
//
viaError += dve_drc(contains(viaGateMetal, viaMetal0) < 1, 
        "Metal 0 Inclusion in Gate Metal min is 1 um");

You can use the poly_inter_layer to detect whether two polygon layers overlap in a wrong manner. The command selects polygons by filtering in or out the overlapping conditions, such as Inside, Outside, Touch, and Cut, and then sends the polygons through an all_edges command to a DRC error layer. For more details, see poly_inter_layer().

Using Rule Conjunction

In general, the result of deriving a work layer from one rule command and later feeding that work layer to another rule command is the combining of more than one rule constraint. This is called rule conjunction. In fact, you have seen rule conjunction in earlier examples of polygon selection commands. Here a more complicated example shows how to use rule conjunction to check Gate Metal manufacturing rules.

// declare output layer
decl gateMetalError = dve_export_layer(120);
//
// Gate Metal spacing Rule
// Rule L - Min. spacing is
//         1.0 if width < 1.5
//         1.5 if 1.5 <= width < 2.0
//         2.0 if 2.0 <= width < 3.0
//         3.0 if               width >= 3.0 

// declare some work layers

decl gatMet15Lt, gatMet15Ge, gatMet20Lt, gatMet20Ge;
decl gatMet30Lt, gatMet30Ge;

// Rule: Min. spacing is 1.0  if width < 1.5
// 1. select the edges with width < 1.5 from gateMetal, save in 
//       gatMet15Lt
// 2. select the edges with spacing error by checking the distance 
//        between gateMetal and gatMet15Lt

gatMet15Lt = dve_drc(width(gateMetal) < 1.5);
gateMetalError += dve_drc(external(gateMetal, gatMet15Lt) < 1.0,
        "Gate Metal min spacing 1.0um when its width < 1.5um");

// Rule: Min. spacing is 1.5  if  1.5 <= width < 2.0
// 1. select the edges with width >= 1.5 from gateMetal, save in 
//        gatMet15Ge
// 2. select the edges with width < 2.0 from gatMet15Ge, save in 
//        fateMet20Lt
// 3. select the edges with spacing error by checking the distance 
//        between gateMetal and gatMet20Lt

gatMet15Ge = dve_drc(width(gateMetal) >= 1.5);
gatMet20Lt = dve_drc(width(gatMet15Ge) < 2.0);
gateMetalError += dve_drc(external(gateMetal, gatMet20Lt) < 1.5,
        "Gate Metal min spacing 1.5um when its width within [1.5, 2)");

// Rule: Min. spacing is 2.0  if  2.0 <= width < 3.0
gatMet20Ge = dve_drc(width(gateMetal) >= 2.0);
gatMet30Lt = dve_drc(width(gatMet20Ge) < 3.0);
gateMetalError += dve_drc(external(gateMetal, gatMet30Lt) < 2.0,
        "Gate Metal min spacing 2.0um when its width within [2.0, 3)");

// Rule: Min. spacing is 3.0  if width >= 3.0
gatMet30Ge = dve_drc(width(gateMetal) >= 3.0);
gateMetalError += dve_drc(external(gateMetal, gatMet30Ge) < 3.0,
        "Gate Metal min spacing 3.0um when its width > 3.0 um");

Congratulations. You have finished writing your first rule file. If you would like to save it to a file, remember to use the file extension .ael. For details, see Saving a DRC Rule.