Glossary for RFIC Dynamic Link

ADS (Advanced Design System)

Advanced Design System is an EDA System for high-frequency circuit and system design.

AEL (Cadence Analog Expression Language)

In the Cadence context, AEL is the syntax and API (available in Skill or C) to support full or partial expression evaluation for repetitious circuit simulation.

AEL (ADS Application Extension Language)

This is a C-like interpretive programming language to configure, customize and enhance the Advanced Design System design environment.

Affirma Analog Circuit Design Environment

Cadence's interface for analog circuit design and analysis in versions 4.4.5 and 4.4.6.

bindkeys

Settings used to map individual keystrokes to a particular function within the software.

callback

A function or expression that gets evaluated when certain events occur; for example, clicking on a menu item.

CDF (Component Description Format)

The CDF is Cadence's mechanism to interactively define and evaluate parameters and attributes for individual components and designs.

CIW (Command Interpreter Window)

The CIW is Cadence's command window.

colormap

Indexed color table where each entry is a combination of R, G, and B pixel intensity values for UNIX X-windows display. Table size (number of colors) per software application is limited by the number of display bits per pixel, commonly eight.

DFII (Design Framework II)

Cadence's overall IC design environment.

EDA (Electronic Design Automation)

Software and services that give customers a distinct advantage by improving time-to-market, quality and productivity in the design of electronic products.

GUI (Graphical User Interface)

The interface between the user and the application.

HB (Harmonic Balance Simulation)

An iterative method of analysis that is based on the assumption that for a given sinusoidal excitation, there exists a steady-state solution that can be approximated to satisfactory accuracy using a finite Fourier series.

iPar()

The function used in an AEL expression for a parameter which is a function of another parameter of the same instance. For example, for MOSFET instances we might use AD=iPar("w")*5u.

IPC (Inter-Process Communication)

The protocol for passing messages between two or more processes.

OASIS

Open Analog Simulation Integration Socket. The procedural interface for simulator integration into the Cadence simulation environment.

optimization

Mechanism by which a simulator finds the optimal value of a global parameter within a user-supplied range of values.

OS (Operating system)

Such as HP-UX, Solaris, or Win2000.

pPar()

The function used in a Cadence AEL expression for a parameter which is a function of some parameter of the parent instance. For example, for CMOS inverters we might use W=pPar(wp) (where wp is a parent instance parameter) on one of the pull-up FETs, enabling use of the same inverter symbol for different size inverters.

PSF

Parameter Storage Format. This is a Cadence-defined file format for storing complex structured data.

Ptolemy

A design environment that supports simultaneous mixtures of different computation models. Ptolemy, named after the second-century Greek astronomer, mathematician, and geographer, was developed at the University of California at Berkeley. For detailed information, refer to the ADS Ptolemy Simulation documentation.

RF Design Environment (RFDE)

RF Design Environment provides a more tightly integrated EDA solution that enables RF/mixed-signal IC designers to simulate their designs directly in the Cadence environment using the ADSsim RF simulator. This enables the RF/MS IC customer to take advantage of complementary features provided by both Agilent Technologies and Cadence Design Systems.

RFIC Dynamic Link (Dynamic Link)

RFIC Dynamic Link (Dynamic Link) for Cadence is an EDA framework integration software product. The product enables both tops-down and bottoms-up design and simulation in Advanced Design System(ADS) using IC designs from the Cadence database. RFIC Dynamic Link is based on IPC rather than data file translation maximizing data integrity and ease of use.

SKILL

Cadence's C/lisp-like interpretive programming language for framework and database integration.

testbench

Top-level schematic used to analyze a sub-circuit using a circuit simulator.

tuning

Mechanism by which a simulator can quickly re-simulate a circuit using new values for a number of parameters without having to re-input the netlist and recreate its data structures.

Virtuoso Analog Design Environment

Cadence's analog design and simulation environment for the Virtuoso custom design platform. It is a task-based environment for simulating and analyzing full-custom, analog, and RF IC designs.