Netlisting, Simulating, and Displaying Data

This chapter describes the procedures for netlisting and simulating a design as well as viewing the netlist from either Advanced Design System or a Cadence Schematic window. Information on net, instance and expression name mapping is also provided.

Netlisting and Simulating a Design

Netlisting automatically occurs when you simulate your schematic in Advanced Design System. The complete netlist is sent to the simulator, stored in memory, and written to a netlist.log file in the project directory of ADS. You can view the netlist in the netlist.log file as needed.

To netlist and simulate a schematic in Advanced Design System:

1. In the ADS Schematic window, choose the Simulate icon or choose the menu item Simulate > Simulate .
   A Simulation window appears, indicating the netlisting status and listing any errors encountered. If the netlisting is successful, the design is then simulated; otherwise, act on the errors displayed in the Simulation window and repeat step one above.
2. For information on configuring and viewing the simulation results in the Data Display window, refer to Data Display Basics in the Data Display documentation.

Viewing Netlists

This section describes how to view the top-level netlist from Advanced Design System as well as how to view an ADS subnetwork netlist for a Cadence design from a Cadence Schematic window.

Viewing Netlists from Advanced Design System

To generate and display the entire top-level ADS netlist, select DynamicLink > Top-level Design Netlist .

Viewing Top-Level ADS Netlist

Viewing Netlists from the Cadence Schematic Window

To generate and display the ADS subnetwork netlist for the Cadence design displayed in a particular Cadence Schematic window:

1. From the menu bar, select DynamicLink > Subcircuit Netlist . Netlisting progress is displayed in the Cadence CIW.

   Note If the Dynamic Link pull-down menu does not appear in the Cadence Virtuoso Schematic window, choose Tools > ADS Dynamic Link > Add Dynamic Link menu to all schematic windows in the Cadence Command Interpreter Window (CIW).

   
   

   Viewing a Subnetwork Netlist

2. A log window pops up, displaying the netlist results. Once you have viewed the results, you can select File > Close Window to exit this window.

Net and Instance Name Mapping

Since Advanced Design System nomenclature rules differ from those of Cadence, nets, instances, etc. must be properly mapped. This mapping is done automatically as part of the netlisting function. The mapping rules are as follows.

• Advanced Design System keywords used as net or instance names are mapped by appending an underscore (_) to the name.

  Name	Map
  then	then_
  else	else_
  elseif	elseif_
  endif	endif_
  equals	equals_
  notequals	notequals_
  and	and_
  not	not_
  or	or_
  global	global_
  model	model_
  define	define_
  end	end_
  parameters	parameters_

• Any non-alphabetical character (e.g. not a-z) in a net or instance name is mapped to an under bar (_).
• Advanced Design System uses a single name space for all names, regardless of object type (net, instance, etc.). This may necessitate name mapping in addition to the above.

Expression Name Mapping

Most Cadence Analog Expression Language (AEL) expressions contain constants, functions and suffixes with equivalents in ADS. In most cases the names of these equivalents are identical, requiring no mapping. As far as possible, Cadence expressions are pre-evaluated in the Cadence environment, prior to netlisting and prior to getting design variables from Cadence. This leaves only a few built-in function names to map (i.e. names that are not identical in the two environments).

Cadence	ADS
complex	cmplx
fabs	abs
log	ln
log10	log

Some built-in operator and function names in the Cadence Affirma Analog Circuit Design Environment as yet do not map to anything in the ADS environment.

Non-Mapping Operators

Cadence	Description
-	unary minus
~	unary one's complement
%	modulo
<<	left shift
>>	right shift
&	bitwise AND
|	bitwise OR
^	bitwise XOR
?:	conditional expression

For these non-mapping functions, custom equivalents in ADS need to be written and mapped until they are available as built-ins in ADS. Custom mapping is enabled via the configuration file option IDF_EXPR_MAP. For more information, refer to Expression Mapping in Modifying the Configuration File.

Non-Mapping Functions

Cadence	Description
acosh	inverse hyperbolic cosine
asinh	inverse hyperbolic sine
atanh	inverse hyperbolic tangent
aelCheckRange	determines if a number falls within a range
conjgate	complex conjugate
floor	floor of a real number
ceil	ceiling of real number
mag	magnitude
db10	10 times log10
db20	20 times log10

Using Global Nodes

Cadence designs typically use implicit global nodes (names ending in ! ) for substrate power and ground connections. This notation is now supported by Advanced Design System. If the exclamation point suffix is used, a globalnode does not need to be placed in the ADS schematic.