Running a DSP and Analog/RF Cosimulation with RFIC Dynamic Link

This chapter describes how to run cosimulation of behavioral Digital Signal Processing (DSP) designs along with Analog/RF circuit designs. Using RFIC Dynamic Link, you can perform a cosimulation with DSP designs in Advanced Design System (ADS) and your Analog/RF designs in Cadence. To run a cosimulation using RFIC Dynamic Link, you will need to create an intermediate layer ADS design. This intermediate design must contain a dummy ADS design representing the Cadence cellview in ADS and also include either an ADS Transient (Tran) or Envelope simulation controller.

For more detailed information about ADS Cosimulation, refer to the ADS Ptolemy Simulation documentation.

RFIC Dynamic Link DSP and Analog/RF Cosimulation Example

The following example uses the RectifiedCx design (see the following figure) provided in the ADS Communication Systems RectifierCosim_prj example project to demonstrate running a DSP and Analog/RF cosimulation using RFIC Dynamic Link.

Communications Systems RectifiedCx Example

The intermediate ADS design used in this example is a modified version of the rct_Env subcircuit design called rct_Env_Cadence (see the following figure).

The rct_Env_Cadence Intermediate Design

Before you begin, ensure you are set up to run the RFIC Dynamic Link examples as described in Setting up the Examples Directory.

1. Open the rct cellview under the examples library. This cellview is a duplicate of the Advanced Design System rct_Env.dsn in the ADS example project $HPEESOF_DIR/examples/Com_Sys/RectifierCosim_prj.

   Note As an alternative to performing steps 2 to 4 below, you can simply execute the get_cosim_example.sh script in the examples directory at your system prompt.

   
   

   The rct Cell in the examples Library

2. Copy the ADS example project $HPEESOF_DIR/examples/Com_Sys/RectifierCosim_prj to a local directory.
3. Copy $HPEESOF_DIR/idf/examples/examples_prj/networks/rct_Env_Cadence.* to the local RectifierCosim_prj/networks directory. This is the intermediate ADS design for this example.
4. Copy $HPEESOF_DIR/idf/examples/models/diodem2.ads to the local RectifierCosim_prj directory. This model file contains the same ADS netlist as generated for the diode DIODEM2 in the original rct_Env subcircuit.
5. Start ADS by selecting Tools > ADS Dynamic Link in the Cadence schematic window.
6. Open the local RectifierCosim_prj from the ADS Main window, then open the rct_Env_Cadence ADS design.
7. Choose DynamicLink > Instance > Add Instance of Cellview to place the examples_rct_schematic design between the two ports.
8. Add a NetlistInclude component to the rct_Env_Cadence design by choosing DynamicLink > Add Netlist File Include .
9. Double click the NetlistInclude component and apply the diodem2.ads model file to the IncludeFiles parameter.
   
   

   Adding the NetlistInclude Component

10. Click OK to update the NetlistInclude component. The modified rct_Env_Cadence design should now appear similar to the following figure.
    
    

    The Modified rct_Env_Cadence Design

11. Replace the rct_Env subcircuit component with rct_Env_Cadence in the RectifiedCx design by choosing Insert > Component > Component Library and then selecting the rct_Env_Cadence from the Library Browser.

    Note If a Failed to locate the component definition error occurs, you may need to create a symbol. Open the rct_Env_Cadence design and select View > Create/Edit Schematic Symbol to create a new symbol.

    
    

    The RectifiedCx Design with rct_Env_Cadence

12. Choose Simulate > Simulate in the ADS schematic window of RectifierCx to simulate the design in ADS.
    Simulation results of the modified RectifierCx design with rct_Env_Cadence subcircuit should be identical with that of the original RectifierCx Design where the rct_Env subcircuit was included.