Using Additional Features of RFIC Dynamic Link

This chapter describes some of the additional features provided by the RFIC Dynamic Link. Some of the issues related to compatibility between Advanced Design System and the Cadence tools are also discussed in this chapter.

Freezing Selected Subcircuits

The RFIC Dynamic Link Freeze mode enables you to keep Cadence from generating a new netlist each time you simulate in Advanced Design System. This helps to avoid unnecessary time-outs caused by re-netlisting a large Cadence subcircuit.

Setting the Freeze Parameter

If you want to keep a Cadence Cellview from being netlisted and a netlist already exists:

  1. Edit the ADS dummy design for that Cellview which would have a name of the form < lib >< _cell >< _view >.dsn. In this example, the name of the file is examples_PowerAmp_schematic.
  2. Double click the _
    idfSymbol_ in the schematic dummy design (see the following figure) and set the freeze parameter to "yes" or "TRUE". Note that the idfSymbol contains the library name, cell name, view name and netlist file information

Freeze Parameter Setting in idfSymbol

Refer to the example schematic in the following figure for the location of the freeze and netlistFile parameter settings. To turn the freeze parameter off, set the parameter to "no" or "FALSE". The default value for the freeze parameter is "FALSE".

Defining the Freeze Parameter

To freeze all Cadence subcircuits, see Modifying the Configuration File.

Generating a Cadence Subcircuit Netlist

In order to run Dynamic Link in Freeze mode, the Cadence subcircuit netlist must exist. If a Cadence subcircuit netlist does not exist, you can generate a new Cadence subcircuit netlist before running your ADS Simulation. Choose DynamicLink > Subcircuit Netlist from your Cadence Schematic window.

Note
If the Dynamic Link pull-down menu does not appear in the Cadence Virtuoso Schematic window, choose Tools > ADS Dynamic Link > Add Dynamic Link menu to all schematic windows in the Cadence Command Interpreter Window (CIW).

This generates the Cadence subcircuit netlist. You can now run your ADS Simulation in Freeze mode.

Note
If you set the Freeze parameter to TRUE but the Cadence subcircuit has never been netlisted, the Cadence subcircuit will automatically be netlisted the first time an ADS Simulation is attempted.

Setting the netlistFile Parameter

The netlistFile parameter is used to specify the location of the ADS netlist of a frozen Cadence Cellview. On the dummy (placeholder) design, set the netlistFile parameter to point to the appropriate netlist file. For example:

netlistFile="examples_PowerAmp_schematic.net"

The default location for storing the ADS netlist of a frozen Cadence Cellview is:

<current_ADS_project_directory> /networks/

If you want to copy the netlist file elsewhere, set the netlistFile parameter to point to the full path and file name of the new location. For example:

netlistFile="/tmp/my_design.net"

Refer to the example schematic in Defining the Freeze Parameter for the location of the netlistFile parameter setting.

Using "Freeze" Mode to Simulate a Design in ADS Standalone

You can run Advanced Design System standalone (without Cadence DFII or RFIC Dynamic Link) using a frozen netlist from an earlier RFIC Dynamic Link session (see Freezing Selected Subcircuits). The parameter Freeze=TRUE must be set on all dummy designs in ADS that represent Cadence cellviews.

While RFIC Dynamic Link is not designed to operate on a PC, you can take an ADS netlist (created using Dynamic Link on your UNIX workstation) of your Cadence cellview and copy it to your PC for an ADS simulation. This type of operation is typically done for board design. Once you have done some minor configuration, you can then add simulation and control components externally to your design and resimulate on the PC.

To set up and simulate your Cadence cellview in Advanced Design System on a standalone Windows machine:

  1. Install RFIC Dynamic Link on your PC.
  2. For each Cadence CellView, copy the netlist, AEL and design files into your working project directory's networks subdirectory. For instance, copy the following example PowerAmp schematic files into your project directory: 
    examples_PowerAmp_Schematic.net
examples_PowerAmp_Schematic.ael
examples_PowerAmp_Schematic.dsn
  3. If the Cadence CellView contains design variables, you will need to manually enter them into a VAR block in the top level ADS schematic. To do this:
    • Choose Data Items from the Component Pallet.
    • Click the Var Eqn block to add the component and use the cursor to place an instance on the schematic. You may continue placing more instances of the Var Eqn block, or choose the Cancel Command And Return To Select Mode icon to proceed with the next step.
    • Enter the appropriate values into Var Eqn block.

It is important to note that any changes made to the design on your standalone machine will not be reflected in your original Cadence cellview. While you may add simulation and control elements externally, the fundamental design should not be changed if you want it to match your original Cadence design.

Compatibility between Advanced Design System and Cadence Tools

Some of the features provided by the RFIC Dynamic Link include support for compatibility issues related to differences between Advanced Design System and the various Cadence tools. This section addresses several of these compatibility issues.

Support for Duplicate Pin Names

It is typical for the top (chip) level schematic to have multiple pins for the same signal, usually power and ground connections. The netlister lists duplicate I/O ports only once in the subnetwork definition and likewise for the nets connected to an instance of the subnetwork. However, the netlister in ADS (which does the top-level netlisting), writes out the multiple connections to ports with the same name, causing a conflict to be reported by the ADS simulator while parsing the final netlist. To eliminate this conflict, when the symbol generator encounters duplicate pin names, it draws only one pin with a given name and issues a warning message. However, duplicate pins at lower levels in the Cadence schematic hierarchy are allowed, because no ADS symbol is involved.

Using Buses

For an example on using buses in RFIC Dynamic Link, refer to Getting Started Tutorial and use the PowerAmp2 Cadence cellview in place of the PowerAmp cellview. Then use the PowerAmp2_test ADS design in place of the PowerAmp_test design. The PowerAmp2 example is the same as the PowerAmp example except that it uses bus wires.

For details on creating buses in ADS, refer to Chapter 3 of the ["../usrguide/wwhelp.htm"Schematic Capture and Layout] documentation. __ For details on using buses within Cadence Design Framework II, refer to your Cadence documentation.

Setting up Unnamed Nets

In ADS, unnamed nets begin with an _net prefix followed by an integer. All other net value are written out to the output dataset during simulation. By default, Cadence tools use the prefix net followed by an integer. By default, the dataset can get very large. To avoid this, set the Net Name Prefix in the Cadence schematic to _net instead of net .
To set the default Net Name Prefix in the Cadence schematic:

Support for pPar and iPar

This section describes the general use of parent parameters (pPar) and instance parameters (iPar).

pPar()

The following figure shows an example of an inverter design that contains two CMOS transistors (M0 & M1).

Composer Schematic showing use of pPar()

This Composer circuit contains instances whose parameters are defined in terms of parent parameter values using pPar() . The parameters in this case are defined as,

l = pPar("ln")

w = pPar("wn")

for M0, and

l = pPar("lp")

w = pPar("wp")

for M1.

This inverter circuit also has an associated symbol view in Cadence Composer. The symbol view shown in the following figure is equivalent to a black box that displays the input, output and instance properties for the circuit in the previous figure.

The default values of wn , ln , wp and lp are displayed in the symbol view along with the associated symbol for the device.

Composer Symbol View showing default values for pPar()

The Composer symbol is instantiated in ADS via the Dynamic Link where the instance properties also appear in ADS Schematic (see the following figure).

Inherited Symbol in ADS

The parameter values are reflected in the netlist that is sent to the simulator. These values can be viewed and edited using the Cadence Edit Component CDF form (see the following figure).

If the Cadence menu option Design > Create Cellview > From Cellview is used, the CDF for the schematic will be set up automatically. The Cadence software will traverse the hierarchy looking for pPar statements and automatically generate parameters. It will also set up netlisting data for known simulators.

If you are modifying an existing schematic and you have already generated a symbol for your schematic, it may be necessary to manually add the netlisting data for ADS. If this is the case, do the following:

  1. Go to the Simulation Information section of the Edit Component CDF form (see the following figure) and click Edit .

    Edit Component CDF Form
  2. When the Edit Simulation Information dialog (see the following figure) appears, change the Choose Simulator setting to "ads".

    Edit Simulation Information Dialog
  3. In the netlistProcedure field enter IdfSubcktCall .
  4. In the instParameters field enter the parameters you wish to have netlisted for ADS. For the inv circuit, this means entering "wn ln wp lp". The parameter order does not matter.
  5. Change the componentName field entry to "subcircuit" or leave it blank.
  6. Set the termOrder field to the order you wish to netlist the terminals in for ADS. You should have one entry for each terminal on your design. For the inv circuit, this is set to "in" "out". You can also quote the names, but it is not necessary.
  7. If you wish to back annotate currents, make the appropriate entry in the termMapping field. This is done by specifying the name of a terminal, followed by the ADS pin number it will be. For the inv example, termMapping entry would be "nil in ": P1" out ": P2"".

For more information on editing simulator information, refer to Creating the Netlist Interface in the Cadence Library Integration documentation.

iPar()

Similarly, the Dynamic Link supports the use of iPar . For any given instance, you can define an instance parameter as a function of another parameter of the same instance. For example, if the parameter w in the figure Composer Schematic showing use of pPar() were defined as w=2*iPar("l"), then if l=10, then w=20.

Using Inherited Connections

Inherited connections used in Dynamic Link must all be resolved within the Cadence hierarchy. For example, if you create a schematic in Cadence called test , that contains instances that have inherited connections with them, such as nmos in analogLib, the default connectivity is used in test if no netset properties have been placed on instances in the hierarchy of the top level circuit. If you have hierarchy above the top level Cadence schematic placed in the ADS design environment, you cannot place netset properties on those instances.

Using S-parameter File Devices from analogLib

For information on S-parameter file components in the analogLib library, refer to Using S-parameter File Devices from analogLib in the analogLib Components documentation.

Encoding Cadence Designs for RFIC Dynamic Link

This example demonstrates the use of Advanced Design System's RF IP Encoder command-line interface with RFIC Dynamic Link. The Cadence and ADS designs provided in the RFIC Dynamic Link Tutorial are adopted here. The PowerAmp Cadence design and the ADS model files that are used in the design will be encoded using the RF IP Encoder, as a component in an ADS library. The encoded component will eventually be used in the PowerAmp_test ADS design for a simulation. For more information, refer to the RF Intellectual Property Encoder documentation.

Familiarity with the Cadence environment and the RFIC Dynamic Link tutorial is assumed. The RFIC Dynamic Link tutorial is provided in Getting Started Tutorial.

The following is a list of steps to encode a Cadence design and then use the encoded design in an ADS simulation via RFIC Dynamic Link:

  1. Make a copy of the Dynamic Link examples directory and start Cadence from the directory created. For example, enter the following commands: 
    cp -r $HPEESOF_DIR/idf/examples /tmp
cd /tmp/examples
icms&

    See Setting up the Examples Directory for details.

  2. Open the PowerAmp cellview of the examples library in the Cadence schematic window.
  3. Choose Tools > ADS Dynamic Link menu item in the Cadence schematic window to start ADS RFIC Dynamic Link.
  4. Choose DynamicLink > Subcircuit Netlist menu item in the Cadence schematic window to generate the netlist for the PowerAmp Cadence design.
  5. Choose File > Save As in the netlist window and save the netlist file as examples_PowerAmp_schematic . For demonstration purpose, it is more convenient to name the netlist file exactly as examples_PowerAmp_schematic here, i.e. name the netlist file as <libName> _ <cellName> _ <viewName> with no extension.
  6. Close the Cadence schematic window and the netlist window.
  7. Open the examples_PowerAmp_schematic file in an ACSCII text editor.
  8. Insert the two model files examples/models/npnpwa1.ads and examples/models/npnpwa2.ads between the end and the #endif statements in the examples_PowerAmp_schematic file as shown below. Save your changes and quit the editor. 
    ...
end examples_PowerAmp_schematic
model npnpwa1 BJT NPN=1 PNP=0 Bf=130 Ikf=0.01085 \
    Ise=7.56E-13 Ne=2 Vaf=25 Nf=1.03 Tf=8.91E-12 \
    Xtf=3.35 Vtf=0 Itf=0.0217 Ptf=18 Xtb=2.2 \
    Approxqb=1 Br=5.123 Ikr=0.056 Isc=2.01E-12 \
    Nc=2 Var=0 Nr=1 Tr=1.6E-9 Eg=1.11 Is=2.15E-16 \
    Imax=1 Xti=8 Tnom=25 Nk=0.5 Iss=3.28E-13 Ns=1 \
    Cjc=1.045E-13 Vjc=0.75 Mjc=0.5 Xcjc=0.2292 \
    Fc=0.5 Cje=1.935E-13 Vje=0.85 Mje=0.4 \
    Cjs=1.092E-13 Vjs=0.7 Mjs=0.5 Rb=317 Irb=0 \
    Rbm=10.63 Re=1.79 Rc=37.6 Af=1 Ab=1 \
    Fb=1 Ffe=1 Lateral=0 
model npnpwa2 BJT NPN=1 PNP=0 Bf=166 Ikf=0.02325 \
    Ise=1.218E-12 Ne=2 Vaf=25 Nf=1.03 Tf=7.97E-12 \
    Xtf=3.16 Vtf=0 Itf=0.0465 Ptf=18 Xtb=2.2 \
    Approxqb=1 Br=5.123 Ikr=0.12 Isc=4.08E-12 \
    Nc=2 Var=0 Nr=1 Tr=1.6E-9 Eg=1.11 Is=4.08E-16 \
    Imax=1 Xti=8 Tnom=25 Nk=0.5 Iss=4.96E-13 Ns=1 \
    Cjc=2.13E-13 Vjc=0.75 Mjc=0.5 Xcjc=0.22 \
    Fc=0.5 Cje=3.123E-13 Vje=0.85 Mje=0.4 \
    Cjs=1.65E-13 Vjs=0.7 Mjs=0.5 Rb=59.2 Irb=0 \
    Rbm=14.1 Re=0.833 Rc=22 Af=1 Ab=1 \
    Fb=1 Ffe=1 Lateral=0 
#endif
  9. Make a temporary working directory. For example, enter 
    mkdir /tmp/myip
cd /tmp/myip
  10. Copy the netlist fragment to be encrypted to the temporary directory. Make sure the filename is the name that will be used to get the fragment out of the library and it does not contain an extension. For example, enter 
    cp /tmp/examples/examples_PowerAmp_schematic /tmp/myip/
  11. Create a new file named 'library.cfg' that contains the following three lines: 
    Library name: PowerAmp_schematic
Library size: 2
examples_PowerAmp_schematic examples_PowerAmp_schematic
  12. Create another file named `ADSlibconfig' that contains the following line: 
    PowerAmp_schematic /tmp/myip/PowerAmp_schematic.library
  13. Make sure LD_LIBRARY_PATH (Linux and SunOS) or SHLIB_PATH (HP-UX) is set to include shared libraries required to run ADS. For example, entering the following command at the Korn shell prompt will accomplish this: 
    . bootscripts.sh
  14. Make sure PowerAmp_schematic.library does not already exist by entering: 
    rm PowerAmp_schematic.library
  15. Enter the `hpeesofencode' command to create PowerAmp_schematic.library.
  16. Edit or create one of three ADSlibconfig files to add a line for mapping the library name to the full path to the .library file. The line to add for this tutorial should read: 
    PowerAmp_schematic /tmp/myip/PowerAmp_schematic.library

    The library mapping line can be added to any of the three ADSlibconfig files listed below:

    $HOME/hpeesof/circuit/config/ADSlibconfig
$HPEESOF_DIR/custom/circuit/config/ADSlibconfig
$HPEESOF_DIR/circuit/config/ADSlibconfig
  17. Choose File > New > Cellview in the Cadence CIW to create a new examples_PowerAmp_schematic symbol in the examples library, that is, enter the following information in the Create New File form:
    Library Name: examples
    Cell Name: examples_PowerAmp_schematic
    View Name: symbol

    Note that selecting Composer-Symbol in the Tool cyclic button will fill in symbol as the View Name.

  18. In the Cadence Symbol Editor window, choose Add > Import Symbol to import the PowerAmp symbol in the examples library. Save the symbol and close the Symbol Editor window.
  19. Use the Cadence CDF Editor or cdfDump() and load() SKILL commands to enter the following ads simInfo (Simulation Information) for the examples_PowerAmp_schematic cellview:
    netlistProcedure ADSsimCompPrim
    termOrder (GND VCC1 VCC2 Vin Vout)
    uselib PowerAmp_schematic

    Note that the library name entered in the uselib field must be exactly the same as the name entered in the ADSlibconfig file.

  20. Create an ads view by copying the examples_PowerAmp_schematic symbol view to an ads view. One way is to press and hold the middle mouse button at the symbol in the Cadence Library Manager and select Copy in the popup menu. Enter ads in the View field of the To group in the Copy View form and click OK .
  21. Create a cellview in the Cadence schematic window. For example, enter the following information in the Create New File form:
    Library Name: examples
    Cell Name: trojan
    View Name: schematic
  22. Place an examples_PowerAmp_schematic instance in the schematic window. Add five Input/Output pins and connect one to each pin of the instance as shown below.
  23. Choose Tools > ADS Dynamic Link in the Cadence schematic window.
  24. Choose DynamicLink > Design Variables in the Cadence schematic window in which the trojan cellview is displayed. Add the following four design variables:
    Rout 12
    Rcc 10
    Remitin 200
    Remitout 163

    It may be necessary to click the Copy To button in the Design Variables form.

  25. Choose Design > Create Cellview > From Cellview to create a symbol view for the examples/trojan/schematic cellview. Save the symbol created and close the Symbol Editor window.
  26. Click the Check and Save icon in the schematic window.
  27. Open the PowerAmp_test ADS design in the examples_prj ADS project.
  28. Choose DynamicLink > Instance > Add Instance of Cellview to place the examples_trojan_schematic instance in the PowerAmp_test ADS design. Make an appropriate connection for each of the five pins as demonstrated in the Dynamic Link Tutorial. Make sure the v1 pin, which connects to the VCC1 pin of the examples_PowerAmp_schematic Cadence cellview, is connected to the SRC1 instance on the right side of the PowerAmp_test ADS design.
  29. Choose DynamicLink > Design Variables > Get Design Variables to add the Rout, Rcc, Remitin, and Remitout Cadence design variables to the VAR1 block in the ADS schematic window.
  30. Activate the DC and S_PARAMETERS simulation controllers and start an ADS simulation.
    Note
    Unlike in the Dynamic Link Tutorial, the model cards need not be included in a NetlistInclude component since they have already been included in the encoded PowerAmp_schematic library.
  31. Plot S(2,1) to ensure the simulation results are the same as illustrated in the Dynamic Link Tutorial. If the simulation completed without error but the output plot looks different, check the pin order of the Cadence instance.
  32. Choose DynamicLink > Top-level Design Netlist in the ADS schematic window and observe the following lines in the netlist file: 
    define examples_trojan_schematic \( gd v1 v2 vi vo \)
#{anchor:1109884:index:uselib}uselib "PowerAmp_schematic", "examples_PowerAmp_schematic"
examples_PowerAmp_schematic:I0 gd v1 v2 vi vo
end examples_trojan_schematic
...
examples_trojan_schematic:X1 0 net51 net50 net54 net52

    These lines are equivalent to the combination of the subcircuit call, the subcircuit definition of the examples_PowerAmp_schematic, and the model card include statements in the netlist of the Dynamic Link Tutorial.

  33. Choose DynamicLink > Close Connection to end the Dynamic Link session. Exit Cadence.

Encoding Process Summary

When selecting the DynamicLink > Subcircuit Netlist menu item in a Cadence schematic window, Dynamic Link defines the Cadence subcircuit name as <libName> _ <cellName> _ <viewName> , which can be renamed as desired in an editor. The key is that a Cadence component with the same name as the subcircuit, with an ads view and appropriate uselib, must be created. The name must contain an underscore character. The whole string with the underscore character will be the encoded component name. The sub-string after the underscore will be the name of the new ADS library that contains the encoded component.

If the Simulation > Netlist > Recreate menu item in the RF Design Environment (RFDE) Analog Design Environment is used to create the initial netlist, a subcircuit definition (define <subckt_name> and end statements) must be inserted and undesired netlist fragments such as, Options and outputPlan, must be removed.

The encoded design will not work in spectre or other simulators integrated into the Cadence design environment.

In summary, here is the list of tasks to perform for creating and using an encoded Cadence design with Dynamic Link or RFDE:

  1. Create a subcircuit netlist for the Cadence design to be encoded. The subcircuit name must contain an underscore character. For the ensuing context, assuming ABC_XYZ is the subcircuit name.
  2. Merge model cards to be encoded with the above netlist file and save the file as the same name as the subcircuit with no suffix, i.e. ABC_XYZ.
  3. Create a `library.cfg' file in a temporary working directory with the following three lines: 
    Library name: XYZ
Library size: 2
ABC_XYZ ABC_XYZ
  4. Create another file named `ADSlibconfig' under the same temporary directory with the following line: 

    XYZ _<full_path_to_temporary_directory>_ /XYZ.library

  5. Create a Cadence symbol with as many input/output pins as the encoded subcircuit. This symbol should bear the same name as the subcircuit, i.e. ABC_XYZ.
  6. Enter . bootscript.sh to set up shared library paths for ADS tools.
  7. Enter `hpeesofencode' in the temporary directory to encode the ABC_XYZ netlist file into XYZ.library.
  8. Copy the Cadence symbol view to create an ads view to indicate it being a primitive component in RFIC Dynamic Link and RFDE.
  9. Add an ads simInfo section to the CDF of the Cadence component. Enter ADSsimCompPrim as the netlistProcedure, the encoded library name (i.e. XYZ) as uselib, and appropriate termOrder entries that match the subcircuit definition.
  10. Create a Cadence subcircuit to encapsulate an instance of the above primitive component. This step is not necessary for RFDE.
  11. Instantiate an instance of the Cadence subcircuit cellview in the ADS schematic window via RFIC Dynamic Link to use the encoded Cadence design in ADS; or, simply instantiate an instance of the Cadence primitive component (i.e. the ABC_XYZ symbol) to use the encoded Cadence design in RFDE.
  12. To distribute the encoded design to RFIC Dynamic Link users, deliver the encoded library (XYZ.library), the primitive cellview (ABC_XYZ), and the Cadence wrapper subcircuit created for encapsulating the primitive cellview. For RFDE users, only the first two items are necessary. The original Cadence design and its associated model cards are protected in the encoded library.
    Note that the user of the encoded library will need to add an entry with appropriate full path to define the encoded library in one of the user's three ADSlibconfig files listed below: 
    $HOME/hpeesof/circuit/config/ADSlibconfig
$HPEESOF_DIR/custom/circuit/config/ADSlibconfig
$HPEESOF_DIR/circuit/config/ADSlibconfig
    Note
    The contents of these ADSlibconfig files must contain only ASCII text. Some Windows applications may introduce invisible encoding characters without your knowledge. These non-ASCII endcoding characters will cause a library name to be interpreted incorrectly resulting in a failure that may be very difficult to diagnose. It is highly recommended that you use an ASCII text editor such as vi or emacs to edit these files.

    If you will deliver the library to users who will only use it on a PC, then instantiate the Cadence wrapper instance in an ADS schematic window via Dynamic Link, and then set its Freeze Mode to yes after generating its ADS netlist. You can create an ADS project with a design containing this instance and its design variables (in VAR1), place the encoded library under this ADS project, and then send this ADS project to your users. You will not need to send the Cadence library for PC (Dynamic Link Freeze Mode) users. The ADS design should contain:
    <lib> _ <cell> _ <view> .dsn,
    <lib> _ <cell> _ <view> .ael, and
    <lib> _ <cell> _ <view> .net
    Note that the <lib> _ <cell> _ <view> .net file is the Cadence wrapper circuit's Freeze Mode netlist.

 

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