Using RFIC Dynamic Link

This chapter describes the procedures for:

• Launching Advanced Design System

• Adding an Instance of a Cadence Design

• Pushing into the Design Hierarchy

• Using Design Variables

• Adding Model Files

• Annotating a Cellview

Launching Advanced Design System

To run Advanced Design System from the Cadence Schematic window using RFIC Dynamic Link:

1. In the Cadence Schematic window, open the desired cellview.
2. Choose Tools > ADS Dynamic Link from the Cadence Schematic window. The Advanced Design System Main window appears in the upper left corner of your screen followed, to the right, by an empty ADS Schematic window (this may take some time).

The Cadence schematic window displays a DynamicLink pull-down menu. This menu provides some familiar, useful Affirma Analog Circuit Design Environment interface functionality. For further information about these options, consult your Cadence documentation.

Note The terminal output ( stderr ) of ADS gets redirected to the file idf.log in the directory in which the Cadence framework is started. Once the link is started, subsequently opening a Cadence design will not involve the overhead of re-starting ADS, but you will need to select Tools > ADS Dynamic Link just to see the DynamicLink pull-down menu.

Adding an Instance of a Cadence Design

To add an instance of a Cadence design to an ADS test schematic, choose DynamicLink > Instance > Add Instance of Cellview .

A dialog box appears, allowing the selection of a Cadence design.

If a symbol already exists for the design in Cadence, the symbol geometry is duplicated in ADS; otherwise the Cadence symbol generator is automatically invoked to generate a Cadence symbol, which is then automatically duplicated in ADS.

If Cancel is selected, or if the configuration file has the entry,

IDF_CADENCE_SYMBOL = FALSE

the ADS symbol generation is automatically invoked (as opposed to the Cadence symbol generation). This generates the symbol in ADS.

Note The generated symbol can be edited and modified if needed. If aesthetics are a concern, it is recommended that the symbol be manually created in Cadence and then automatically replicated in ADS as described above. The symbol of the Cadence design is given the following nomenclature <library> _ <cell> _ <view> . For example, examples_PowerAmp_schematic . There is a skeleton schematic of the Cadence design that also gets created in ADS. This is used as a placeholder to link with the actual Cadence design; you do not need to edit this.

Pushing into the Design Hierarchy

To view a design deeper in the Advanced Design System schematic hierarchy:

1. Select the component you want to push into in the ADS Schematic window.
2. Choose the Push Into Hierarchy icon . This downward arrow icon is located below the Cadence menu item in the tool bar.
3. If the selected component is a Cadence cellview instance, the corresponding Cadence cellview is opened in the Cadence design editor. If this view is already open, it is simply raised to the top of the window stack.

Using Design Variables

This section describes how to add and edit design variables in Advanced Design System and also update your Cadence design variables.

Cadence Affirma Analog Circuit Design Environment design variables are intended to be global in the context of a particular Artist session or Cellview. When you select DynamicLink > Design Variables > Get Design Variables , these variables are automatically mapped to corresponding variables in a VAR component in the Advanced Design System schematic. This mapping ensures that these variables can be used for optimization or statistical analysis in ADS.
All the design variables for each Cadence design are put into a single VAR component. Each time the menu item DynamicLink > Design Variables > Get Design Variables is selected, this component is updated with the most recent values from Cadence.

Adding and Editing Design Variables

To add or edit a design variable for the ADS schematic:

1. From the Cadence schematic menu bar, choose DynamicLink > Design Variables . The Cadence Design Variables form appears.
   
   For more information one using this form, refer to Design Variables and Simulation in your Cadence documentation.
2. In the ADS Schematic window, choose DynamicLink > Design Variables > Get Design Variables . This places a corresponding VAR component on the ADS schematic containing the design variables from Cadence. If the VAR component already exists it is updated only with variables and values that are not already there.
   

VAR Block corresponding to Design Variables

Note There is no way to distinguish a design variable of the same name coming from different Cadence cellviews. If a variable has different values in different cellviews, the value sent to ADS is chosen arbitrarily. Non-alphanumeric characters, like parentheses, in variable expressions must be preceded by a backslash (`\').

Updating Cadence Design Variables

To update your Cadence design variables:

1. In the Advanced Design System Schematic window, choose DynamicLink > Design Variables > Update Design Variables .

   Note Design variables can be used for optimizations and sweeps in ADS. Variables used for this purpose should not be assigned a value or expression in Cadence; the Value (Expr) text entry box should be left blank.

Closing the Cadence Connection

If you have changed your design variables in Advanced Design System and attempt to close the Cadence connection before updating your design variables in Cadence, an Update Design Variables To Cadence message will appear prompting you to update design variables.

Adding Model Files

This section describes how to use the Netlist Include Component in RFIC Dynamic Link. The Netlist Include component is provided as a means of utilizing external files in your design.
For more information on the Netlist Include component, refer to Chapter 5 of the ["../ccsim/wwhelp.htm"Introduction to Circuit Components] documentation.

Adding a Netlist File Include Component

To place an instance of the Netlist Include Component :

1. From the top-level ADS schematic window, choose DynamicLink > Add Netlist File Include . An instance of the NetlistInclude is attached to your cursor.
2. Move the cursor to where you want to place the component, then single click. A Netlist Include symbol is placed on the schematic as shown in the following figure.

The Netlist Include Component Symbol

Note Only one Netlist Include Component can be placed in a Dynamic Link design. This is to ensure that files are not multiply included (this cause's redefinition errors within the ADS simulator).

Accessing the Netlist File Include Dialog

To access and edit information in the Netlist File Include component, double click the Netlist Include component symbol. The Netlist File Include dialog box appears.

Select Parameter

The Select Parameter list box displays a list of three parameters that enable you to create your include definition. Refer to each of the sections listed for detailed information on defining these parameters.

• Set the path to where your model files are located (IncludePath).

• Select the model files to include (see IncludeFiles).

• Enter an optional section designator (see Section (optional)).

• Determine the preprocessor setting (see UsePreprocessor).

IncludePath

The includePath parameter is a space delimited search path that is used to locate included model files. The include path needs to be set up for the simulation machine in order to work properly. However, there is an issue with this. The netlister searches through the include path to find files, and then outputs the values as expanded full paths (the simulator requires this). If the expanded full path on the netlisting machine is different from the expanded full path of the simulation machine, the simulator will not find the file to be included. If you want to do remote simulations, ensure that the expanded full path of your included file is the same on the netlisting machine and the simulation machine. Note that, in directory names, path prefixes such as '.', '..', '~', and '$' all have the usual UNIX interpretation.

To enter a group of include paths:

1. Click the includePath= parameter in the Select Parameter list box.
2. Enter the name of the search path in the Search Path for included files (space delimited) field separating each search path by a space.

IncludeFiles

This parameter enables you to build a list of model files that you want to include.To specify the path and filename of a model file to include:

1. Click the IncludeFiles[n]= in the Select Parameter list box. This activates the Model Library File selection field.
   
2. Click the Browse button. The Select File dialog appears.
   
3. Double-click as needed to locate the directory containing your model file or enter the full path and file name in the Selection field. Click OK to return to the Netlist File Include dialog.
4. Once selected, the filename of the model file is displayed in the Library Model File field. Note that the path is appended to the includePath parameter and the file name is added to the IncludeFile parameter definition.
   Example:

   includePath= Path1 Path2 ... ModelFilePath

   IncludeFiles[ n ]= filename

5. To add additional model files, click Add . This creates additional model file parameter definitions in the Select Parameter list box. Repeat steps 1 through 4 to define the path and file name. You can continue adding model file parameters as needed. You can also use the Cut and Paste buttons to move or delete any model file parameters.

Section (optional)

You may only have a single file for each IncludeFiles[n] parameter - unlike the prior parameters - this is not a space delimited list. Each model file can have a Section designator. This enables you to include only a portion of a model file for corner analysis , provided your model file has been set up properly. The section designator is optional; if it is left empty, the entire file will be included (provided it has no dependencies on needing a particular section set up).
To properly set up a model file to utilize the section directive, you must bracket the sections using #ifdef <section>/ #endif C-Pre-Processor(CPP) directives. The netlister automatically defines and undefines a variable with the name section before and after the #include statement. As an example, if you wanted to have a file with corner cases, and had a Nominal section, you would make the file as follows:

#ifdef Nominal
; Nominal section
R:R1 in out R=50
#endif

If the same library file is named, with a different section, a single #include is generated, with multiple #define statements around it.

UsePreprocessor

The UsePreprocessor parameter defaults to " yes" . Setting this parameter to yes causes a preprocessor directive ( #include ) to be used which results in faster behavior by not copying the full text of the file. This parameter can also be set to no to provide a slower, but more compatible, full-text inclusion behavior.
To set the UsePreprocessor parameter,

1. Click the UsePreprocessor=yes parameter in the Select Parameter field of the Netlist File Include dialog box. The Parameter Entry Mode pull-down menu appears.
2. Click the Parameter Entry Mode pull-down menu in the Netlist File Include dialog box and select the appropriate option.
   
   The UsePreprocessor parameter was developed for delivering increased speed to old ADS designs that use the geminiInclude , spiceInclude or csvInclude component and for delivering increased flexibility to old ADS designs using the idfInclude component.

Display parameter on schematic

The Display parameter on schematic check box in the Netlist File Include dialog box is used to list the individual parameters and their associated values on the schematic. If you want to display the parameters, activate the check box.

Component Options

The Component Options dialog box enables you to change the visibility of the component parameters on a schematic and/or reference items in hierarchical designs. To access the Component Options, click the Component Options button on the Netlist File Include dialog box. A Component Options dialog box appears.

Changing the Visibility of Component Parameters on a Schematic

You can change the visibility status of all parameters of the Netlist File Include component through the Component Options dialog box.

• Set All-Displays all parameters for this component on the schematic. Use this option to display all, or almost all, parameters for this component. To display most-but not all-parameters, select Set All and then go back and turn off the display of individual parameters as desired.
• Clear All-Clears the display of all parameters for this component from the schematic. Use this option to turn off the display of all, or almost all, parameters for this component. To display a small subset of parameters, select Clear All and then go back and turn on the display of individual parameters as desired.

Referencing VAR Data Items and Model Items in Hierarchical Designs

The Scope option applies to the VAR (Variables and Equations) data item and most model items (such as R_Model, BJT_Model, BSIM3_Model). Exception: it does not apply to multi-layer models. Scope indicates the levels, from a hierarchical standpoint, that recognize the expressions defined in the VAR data item or model item.

• Nested-VAR or model item expressions are recognized within the design containing the VAR or model item, as well as within any subnetworks (designs at lower levels) referenced by the design containing the VAR or model item.
  Global-VAR or model item expressions are recognized throughout the entire design, no matter what level in the design hierarchy the VAR or model item is placed.

Summarizing the Netlist File Include Component

For all of the Netlist File Include component parameters, a single include statement is netlisted for each file. The netlister checks to see if a file has already been output, to avoid having multiple definitions of files. The precedence is that model files are output first, so that the segment directives can be placed around the #include .
If you are using the Netlist File Include component, it is not putting out #ifdef <file> statements to further ensure that files are not multiply included. If you use a Netlist File Include component, you should not additionally use other file include components to avoid multiple inclusions which will cause a simulator redefinition error.
Example:

Parameter settings

includePath=". ./models"
definitionFiles="functions.def"
stimulusFiles="vccdef.stim"
modelLibraryFiles\[1\]="resistor.lib Nominal"

Netlist File Output (Note that . is /users/default/default_prj in this example):

#define Nominal
#include "/users/default/default_prj/models/resistor.lib"
#undef Nominal
#include "/users/default/default_prj/models/functions.def"
#include "/users/default/default_prj/models/vccdef.stim"

It is worth noting that, once the Netlist File Include component is netlisted, the simulator makes no differentiation between definition, stimulus, or model files. Each file will generate the #include __ statements.

You may want to use the IncludeFiles parameter for all of your files so that you can put corner case statements into all of your model files.

Annotating a Cellview

This section describes how to annotate your simulation results in Advanced Design System to a Cadence cellview.

Annotating DC Voltages to a Cadence Cellview

To annotate a DC voltage solution in Advanced Design System to the Cadence cellview:

1. In Advanced Design System, set up and simulate your schematic. This schematic must contain a DC Simulation Component as shown in Example setup for DC Simulation.
   
   

   Example setup for DC Simulation

2. Select the schematic symbol in the ADS schematic that represents the Cadence circuit you want to back annotate. For example, the amplifier block in the preceding figure.
3. From the ADS Schematic window, choose DynamicLink > Annotate > Annotate DC Solution to Selected Cellview .
4. The voltages are then displayed on the Cadence schematic as shown in the following figure.
   
   

   DC Voltage Annotation on the Cadence Schematic

   Annotating DC Currents to a Cadence Cellview

   To annotate a DC current solution in Advanced Design System to the Cadence cellview:

1. First annotate the DC voltages as described in Annotating DC Voltages to a Cadence Cellview.
2. From the Cadence schematic window, choose Edit > Component Display . The Edit Component Display Options form appears.
3. Click an instance in the Cadence Schematic window. For this example, Q0 was selected. Note that the title of the Edit Component Display Options form changes to include the component selected. In this case, the title Edit Component `Q0' Display appears.
4. Click the terminal checkbox from the Select Label options. Notice that the form now displays a Terminal Labels section. This section shows that DC and voltage is currently selected as seen in Edit Component `Q0' Display form showing DC Voltage.
   
   

   Edit Component `Q0' Display form showing DC Voltage

5. Click the currents checkbox in the Terminal Labels section of the Edit Component Display form to display currents instead of voltage. The next figure shows the design with the DC currents annotated.
6. Click OK to clear the Edit Component `Q0' Display form.
   
   

   DC Current Annotation on the Cadence Schematic

   Note If you do not select an instance, the library that your changes will apply to will be the library that contains the schematic (i.e. examples for the PowerAmp example). Since the primitives (i.e. the res and npn cells) are not in the schematic's library, you will not see any changes to the annotation if you do not first select an instance from the proper library. The Edit Component Display form enables you to control how labels are displayed for each library, cell and instance in the design.

Displaying Voltages or Currents from a Previous Simulation

To display voltages or currents from a previous simulation:

1. Before displaying voltages or currents you must have annotated a DC solution to the schematic in a prior Cadence session. Follow the instructions for annotating a DC solution (see Annotating a Cellview) to a schematic if you have not already done so.
2. From the Cadence Schematic window, choose Edit > Component Display . The Edit Component Display Options form appears.
   
3. Click Set Simulation Data Directory . The Set Label Display Simulation Data Directory form appears.
   
4. Enter the full path to the Data Directory. This is everything up to the psf directory. The psf directory contains Cadence formatted data. The structure for the path name is,
   < Cadence_project_dir >/< cell_name >/< tool_name >/< view >
   The path for the Data Directory used in the example for DC Voltage Annotation on the Cadence Schematic was,
   ~/simulation/PowerAmp/adsDL/schematic
   The annotation code looks in the psf directory.
5. Click OK in the Set Label Display Simulation Data Directory form.
6. Click OK in the Edit Component Display Options form.

Creating Symbols for Hierarchical Subcircuits with cdsTerm

If you want to annotate a hierarchical Cadence design, you must create a Cadence symbol for the design.
To create symbols for hierarchical subcircuits using cdsTerm :

1. From the Cadence Schematic window, choose Design > Create Cellview > From Cellview . The Cellview From Cellview form appears.
   
2. In the Cellview From Cellview form, ensure the following settings are correct:
   • From View Name - schematic
   • To View Name - symbol
   • Tool / Data Type - Composer-Symbol
     Click OK. The Symbol Generation Options form appears, assuming a symbol does not already exist.
3. In the Symbol Generation Options form, click the Edit Labels checkbox. Your form will display the Label options.
4. In the Symbol Generation Options form, select analog pin annotate from the Label Choice pull-down menu. The Name field should now display cdsTerm("(pinname)").
5. Select all pins from the Apply To drop-down menu and click Add . This generates a new label rule that creates a cdsTerm for each pin. You may alter the location if you choose. The form with all appropriate option settings is shown in the following figure.
   
   

   Symbol Generation Options to create a symbol with cdsTerms on each pin

   For more information on the Symbol Generation Option form, refer to your Cadence documentation.