Basic
INP (Standard Input)
Documentation in this chapter is for translation information/notes only. For more information, please see the GENESYS documentation for this model or refer to the documentation for port in ADS.
| GENESYS Symbol | ADS Component |
|---|---|
| INPUT | Port |
| All other symbols | Port using the Intermediate Subcircuit named genesyslib_INP_<SYMBOL> |
Parameter Mapping
| GENESYS | ADS | Comments |
|---|---|---|
| ZO | See note 1. | |
| PORT | Num | |
| All other ADS parameters are set to their default values. | ||
Notes
- This parameter is ignored unless a TestBench is exported for the schematic. The terminations on the TestBench use the ZO from the ports.
OUT (Standard Output)
Documentation in this chapter is for translation information/notes only. For more information, please see the GENESYS documentation for this model or refer to the documentation for port in ADS.
| GENESYS Symbol | ADS Component |
|---|---|
| OUTPUT | Port |
| All other symbols | Port using the Intermediate Subcircuit named genesyslib_*OUT_<SYMBOL> |
Parameter Mapping
| GENESYS | ADS | Comments |
|---|---|---|
| ZO | See note 1. | |
| PORT | Num | |
| All other ADS parameters are set to their default values. | ||
Notes
- This parameter is ignored unless a TestBench is exported for the schematic. The terminations on the TestBench use the ZO from the ports.
VDC(DC Voltage Source)
Documentation in this chapter is for translation information/notes only. For more information, please see the GENESYS documentation for this model or refer to the documentation for V_DC in ADS.
| GENESYS Symbol | ADS Component |
|---|---|
| VDC | V_DC |
| All other symbols | V_DC using the Intermediate Subcircuit named genesyslib_VDC_<SYMBOL> |
Parameter Mapping
| GENESYS | ADS | Comments |
|---|---|---|
| VDC | Vdc | |
| All other ADS parameters are set to their default values. | ||
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