About HDL Cosimulation

With the ADS HDL Cosimulation feature you can simulate components represented in a hardware description language (HDL) in the same schematic with other ADS components. This integrated capability provides complete design flexibility, and complements other ADS modules, including Digital Filter Designer.

The ability to design all portions of a communications product in one integrated environment can eliminate design errors resulting from disconnects among design teams. By cosimulating with HDL designs, you can easily incorporate your existing HDL intellectual property into new designs.

With HDL cosimulation, you can test hardware defined in HDL with a DSP algorithm, or use an algorithm written in HDL within an existing ADS design. VHDL and Verilog HDL are supported. ADS Ptolemy provides the signal processing simulation, while the Model Sim ^TM HDL simulator from Model Technology Incorporated, Verilog® XL from Cadence® Design Systems, or NC-SIM from Cadence® Design Systems simulates the HDL code. This cosimulation capability in one design environment makes it easy to test HDL components along with complex ADS system designs and see the effect on the entire system.

Important Verilog® XL, and NC-SIM from Cadence® Design Systems are no longer supported on the Windows platform.