Automatic Clock and Set Signals

HDL models that have pins named Clock and Set are treated differently. The HdlCosim component has pins named Clock and Set that are modeled as optional pins, meaning you can leave them unconnected. Clock and Set must be part of your Inputs specification, so that they will be processed as mentioned in the section Inputs.

If you connect any signal to Clock and Set pins, that signal will be passed to the HDL port. If you leave the pins unconnected, the default Clock and Set signals will be driven on the Clock and Set HDL ports.

The default clock is of a 50% duty cycle and has a period equal to the HDL iteration time. The positive clock edge occurs at IterationTime/2. The default value for the Set pin during the first iteration is a logic low at 1/4 times the HDL iteration time, a logic high at 3/4 times the HDL iteration time, and a logic high for iterations after that.

The timing of application of inputs for the HDL code generated for a mixed logic is crucial. For example consider a multiplexer (non-clocked, or in general any combinational logic) followed by a latch (clocked, or any sequential logic). The input multiplexer would be triggered the moment input is applied and would produce results with zero delay. If the following component is a clocked component (for example, sequential logic like a latch), then it will be triggered during the same iteration cycle at the positive edge of the clock. So, in the above example, the multiplexer and the latch will be triggered in the same clock cycle. In the corresponding fixed-point design, the multiplexer followed by a latch (Clock and Set unconnected) would fire the multiplexer in one cycle and the latch in the next, producing a delay of one cycle. The HDL cosimulation results will appear one cycle earlier when compared to the equivalent ADS component simulation results.

To match the results, the inputs to the HDL cosimulation block must be delayed until after the positive edge of the clock or IterationTime/2. The inputs will be applied to multiplexer or combinational logic after the positive clock edge. The latch will latch this result only in the next firing of the HDL cosimulation block or the next positive clock edge (the automatic clock has one positive clock edge per firing).

The delay for each input ports is specified in the parameter InputPhases.