Bidirectional HDL Ports

For a bidirectional VHDL port, two ports are created on the cosimulation model. One port is an input port named <VHDL portname>In, while the other port is an output port named <VHDL portname>Out. The input data on the inout type port is applied by ADS for the first half of the HDL iteration time; the signal value is then changed to a tri-state condition. You can drive the output data on an inout type port only during the second half of the HDL iteration time, when the value has been changed to a tri-state condition by ADS. You must set the inout port to a tri-state condition during the first half of the HDL iteration time period, so that ADS can drive the new input data value on the inout port.

Bidirectional ports are not supported in Verilog cosimulation.