HDL Cosimulation Components and Their Parameters

HDL cosimulation components are available in the HDL Blocks palette or library ( Insert > Component > Component Library > HDL Blocks ). The ModelSim cosimulation component is HdlCosim; the VerilogXL cosimulation component is VxlCosim; and, the NC-SIM cosimulation component is NCCosim.

Some HDL simulators require compiled HDL code before simulation. If the user code has not been compiled, HDL cosimulation can compile the user code before cosimulation or use existing compiled HDL code depending on the HdlSrcFile and HdlLibrary settings. The process is further simplified for ADS-generated Verilog code.

Note NC-SIM cosimulation uses ncverilog for compilation and simulation. For VHDL cosimulation, the VHDL code will automatically be wrapped with a Verilog module. Refer to the NC-SIM manual for information on using ncverilog to simulate VHDL code made part of Verilog code. Also refer to example design iir_lp_ncvhdl.dsn; access this design from the ADS Main window > File > Example Project > SDFHdlCosim > iir_filter_prj.

The components have one multi-input and one multi-output fixed-data type ports. They also have single bit input pins Clock and Set. The Clock and Set inputs are processed only if they are part of the Inputs_parameter_specification;_otherwise_they_are_ignored._If_they_are_part_of_the_Inputs_parameter,_the_behavior_is_the_same_as_explained_previously_in_the_section_Automatic Clock and Set Signals.

Note Clock and Set must not be part of the inputs that are being connected to the multi-input port.

HDL cosimulation models have parameters that enable you to control cosimulation with the HDL simulator. The following sections describe the parameters that require user input.

HdlSrcFile

HdlSrcFile can be specified as follows:

• For user HDL code, the HDL source code file must be specified as shown in example design iir_lp_userhdl.dsn (ADS Main window > File > Example Project > SDFHdlCosim > iir_filter_prj). Here, the HdlSrcFile must be the file that contains the VHDL entity or Verilog module information that you want to cosimulate with.
  • When you use ModelSim cosimulation (HdlCosim) and have not compiled the code, you must specify any other HDL files that the first file in HdlSrcFile depends on. The HDL files can be specified after the first file using space as the separator (see iir_lp_userhdl.dsn in the example project: ADS Main window > File > Example Project > SDFHdlCosim > iir_filter_prj ). The files will be compiled at the beginning of the simulation in the reverse order of the specification. A work library is created automatically under project's data directory where all compiled code is saved.
  • In the case of VerilogXL cosimulation (VxlCosim) and NC-SIM cosimulation (NCCosim), all files required for simulation must be specified as mentioned above. In the case of NC-SIM cosimulation (NCCosim), you can use pre-compiled libraries as described in the NC-Verilog Reference manual.
• For user HDL code that contains a long list of dependency files to be compiled, you can create another file that contains the whole list of files. You must specify that file as the value for the HdlSrcFile parameter using < as the first character followed by the file name. See the specification of HdlSrcFile="< iir_lp_flat.txt " in the example design file iir_lp_confvhdl.dsn ( ADS Main window > File > Example Project > SDFHdlCosim > iir_filter_prj) .
• For user-VHDL code containing a configuration specification in a file different from the file containing the entity specification, and if you want ADS to compile the user code prior to cosimulation, then the file specification order is important. The order is important because ADS compiles the files in reverse order of specification, and the configuration specification file must be compiled after the entity specification file. Therefore, the configuration specification file must be specified prior to the entity specification file. For such a specification to identify the entity specification file, the user-VHDL entity specification file must be preceded with a + character. See example design iir_lp_confvhdl.dsn ( ADS Main window > File > Example Project > SDFHdlCosim > iir_filter_prj) .

Inputs

The Inputs parameter lists the names of the input ports of the HDL model. All the HDL input port names that need to be updated from ADS must be specified.

This list is used to make the input connections between the ADS ports and the HDL ports. The BusMerge component must be used on the input port when there is more than one input to be connected. The first (last) input port in the list is connected to the bottom (top) most input port on the BusMerge, and so on. The BusMerge must have a number of input ports equal to the number of strings specified in the Inputs string array, except if the model has pins named Clock and Set. The BusMerge component must not have pins corresponding to Clock and Set, instead they must be connected to the Clock and Set ports of the ADS HdlCosim component. To use automatic Clock and Set signals, leave the Clock and Set ports unconnected or hanging.

InputPhases

The InputPhases parameter delays the application of the input to the HDL model. It is an array of integers. The time unit is the same as specified by the TimeUnit parameter, described later. The InputPhases parameter specifies the delay for the application inputs during an iteration, as explained in the section Automatic Clock and Set Signals The delay specified for the Clock signal is ignored if the Clock signal is not connected and an automatic clock is being used.

If Clock and Set are unconnected and the InputPhases parameter is not specified, the inputs are automatically delayed for 3/4 times the IterationTime specified during each cycle for the reasons mentioned in earlier section Automatic Clock and Set Signals If any phase delay values are specified by the user, those values will be used.

In the case of the ADS HdlCosim component, the order of the delay specification must be the same as the order of the input names specified in the Inputs parameter.

InputPrecisions

The InputPrecisions parameter specifies the precision and arithmetic type to be used for a particular input.

The order of the precision specification must be the same as the order of the input names specified in the Inputs parameter.

Precision and arithmetic type specification was explained earlier in the section Precision for Bit-Vector Type Ports

Outputs

The Outputs parameter lists the names of the output ports of the HDL model. All HDL output port names that need to be read into ADS must be specified.

This list is used when making the output connections between the ADS Ptolemy ports and the HDL ports. The BusSplit component is used on the output port. The first (last) output port in the list is connected to the bottom (top) most output port on the BusSplit, and so on. The BusSplit component must have a number of output ports equal to the number of strings specified in the Outputs string array.

Note In the case of an inout VHDL port, specify the port name in the Inputs as well as the Outputs parameter.

OutputPrecisions

The OutputPrecisions parameter specifies the precision and arithmetic type to be used for a particular output.

The order of the precision specification must be the same as the order of the output names specified in the Outputs parameter, see Outputs.

Precision and arithmetic type specification was explained earlier in the section Precision for Bit-Vector Type Ports.

HdlModelName

HdlModelName is the name of the HDL entity or module to cosimulate with.

For a Verilog module, specify the module name to cosimulate with. For a VHDL entity you can specify this parameter in the following ways:

• To select an entity that has only one architecture, the syntax is
  HdlModelName="<entity>"
• To select an entity along with a particular architecture when more than one is available, the syntax is
  HdlModelName="<entity>.<architecture>"
• To select an entity along with its configuration specification, the syntax is
  HdlModelName="<entity>+<configuration>"

See example design iir_lp_confvhdl.dsn (ADS Main window > File > Example Project > SDFHdlCosim > iir_filter_prj).

HdlLibrary

The HdlLibrary parameter does not exist for VerilogXL cosimulation (VxlCosim) and NC-SIM cosimulation (NCCosim).

In the case of ModelSim cosimulation (HdlCosim), this parameter specifies the library from which the compiled HDL module or entity must be loaded. This parameter can control the compilation as follows:

• If the code needs to be compiled, HdlLibrary must be empty. This will compile the code under work library. For any subsequent re-simulation of the same design, the HDL code need not be recompiled. To turn off compilation, specify HdlLibrary=work.
• If you have already compiled the code in another library (for example, hdllib) then only the file that has the entity or module specification needs to be specified for HdlSrcFile, and HdlLibrary should be set to hdllib.
  • Before starting ADS, the MODELSIM environment variable must be set to a modelsim.ini file that has the mapping information for hdllib.
  • If MODELSIM is not set, you can specify the mapping for the library using =, for example HdlLibrary="hdllib=/user/xyz/hdllib". You can specify more than one library by separating them using spaces, and can specify mappings for any of the libraries using =.

HdlSimulatorGUI

The HdlSimulatorGUI parameter determines the user interface mode of the HDL simulator. If the HdlSimulatorGUI is On, the HDL simulator is started with its graphical user interface on. You can view the progress of the simulation, graph signals, and edit values while the simulation is running.

The ModelSim command Restart is not supported during cosimulation. To restart HDL cosimulation, quit and restart the ADS simulation.

Note If the HdlSimulatorGUI is On and IterationTime is negative, use run -all in ModelSim to perform cosimulation. The other run commands will only increment the HDL simulation time and will not cosimulate.

If the HdlSimulatorGUI is Off, the simulator is run in the background. ADS will start the HDL simulator, run the simulation, and close the simulator at the end of simulation without user interaction.

CmdArgs

The CmdArgs parameter specifies special simulator command invocation arguments required for simulation of the HDL model.

IterationTime

IterationTime is the time that the HDL simulation is run during each firing of the HDL cosimulation component. If the integer value provided is positive, the HDL simulator will simulate for the specified number of time units (where the time units are specified by the parameter TimeUnit) then send data to ADS. This does not check to see if there are any events still to be processed in the simulator. This feature is useful if you are running a model whose output data is to be sampled periodically at a predetermined time.

Note The value can never be specified as 0 because the simulation will stop with a range error flagged.

Negative iteration time is valid only for ModelSim VHDL cosimulation. If the value is negative, the HDL simulator is run until all the events are processed. The magnitude of the value specifies the minimum amount of time to run before checking to see if there are any events still to be processed. The output data is read after the event queue becomes empty. This facility can slow down the simulation due to the overhead of monitoring the simulation event queue. The lower the magnitude, the slower the execution because the event queue must be polled more often. This facility is useful when the time the model takes to provide stable/correct data output varies. This will not work for certain models that never run out of events, such as those with internal clock signals.

When a negative iteration time is specified for a Verilog module to be cosimulated using ModelSim, a VHDL wrapper is used to instantiate the Verilog module.

Note Negative iteration time will not work with Cadence NCsim or VerilogXL cosimulation.

TimeUnit

The TimeUnit parameter specifies the HDL simulation time resolution unit: fs, ps, ns, us, ms or sec.

For VHDL simulation using ModelSim, TimeUnit will control the VHDL simulation time resolution.

For Verilog simulation with any supported HDL simulator, TimeUnit will add timescale directives to the top-level cosimulation wrapper. Users can have timescale directives for different modules in their code. If any user module does not have a timescale specified, TimeUnit will be used to generate a default timescale. The smallest of the different timescale specifications will control the Verilog simulation time resolution.