Precision for Bit-Vector Type Ports

Bit-vector type HDL ports that get mapped to fixed type ports require precision for data conversion. The precision for inputs and outputs is specified in the parameter named Inputs and Outputs.

The precision for a port is specified as two integers separated with a dot (for example 2.14). The first part is the number of bits used for representing the integral part and the second is the number of bits used for representing the fractional part of the value on the port.

By default, the arithmetic type is two's complement. To specify an unsigned arithmetic type, append u to the precision specification. For example, an unsigned 2.14 can be specified as 2.14u.

To repeat a particular precision specification you can use square bracket notation. For example,

2.14u 2.14u 2.14u 1.2 3.4 3.4

can also be represented as

2.14u[3] 1.2 3.4[2]

The least significant bit (LSB) of the fixed data will always be assigned to the lowest indexed element, and the most significant bit (MSB) will always be assigned to the highest indexed element of the HDL vector port. Since the fixed data bit has only two possible values (0 and 1) the values x, u, z, -, w, and l for 9-state std_logic types are mapped to 0 and the value h is mapped to 1.