Theory of Operation for HDL Cosimulation

With the HDL cosimulation feature, ADS Ptolemy has been configured to cosimulate with either the ModelSim, VerilogXL, or NC-SIM HDL simulator. In this use model, you first create the HDL design. The design must be compiled and it is recommended to test the simulation with ModelSim, VerilogXL, or NC-SIM before cosimulation.

If the code is not compiled, you can use ADS to compile the code before cosimulation. Cosimulation requires information regarding the VHDL entity or Verilog module that you want to cosimulate with. This is used to generate HDL wrappers that incorporate user code and C-interface code to create an inter-process communication (IPC) link between ADS and the HDL simulator.

The cosimulation can be run in graphical user interface mode to monitor the HDL simulation. It can also be run in the background processing mode.

HDL cosimulation uses the ADS Ptolemy Synchronous Dataflow (SDF) domain, in which numeric signals are consumed and produced by the HDL cosimulation component. There is no timing information communicated between ADS and the HDL simulator. ADS sends data into the HDL simulator and receives data without any knowledge of the HDL timing.

HDL cosimulation does not use the ADS Ptolemy Timed Synchronous Dataflow (TSDF) domain. Since the HDL cosimulation component acts as an ADS Ptolemy numeric component, any timed data from other ADS Ptolemy components will be converted to numeric at the HDL cosimulation component's input.

The HDL cosimulation component is a numeric component. Because the HDL simulation is time driven, it is initiated at every fixed interval for each firing of the HDL cosimulation component in ADS. The time scale used by the HDL simulator is independent of the ADS simulation.

Each time the HDL cosimulation component is fired, the HDL simulator receives input values from other ADS components and uses them to perform the HDL simulation. Once the HDL simulator is finished with its processing, it passes the simulation results back to ADS. These passed values are then the inputs for other ADS components, and thus the simulation cycle continues. This cycle repeats as many times as the scheduler requires. Each time the HDL cosimulation component is fired, the HDL simulation duration is determined by the value of the IterationTime parameter (see IterationTime) in the HDL cosimulation component. You must determine how long the HDL simulator should run before its outputs are sent back to the HDL component. This timing information should not be confused with the timing used in other ADS Ptolemy timed components.

From the HDL simulator engine's point of view, the ADS input interface is viewed as forcing values onto the ports. At the output interface of the HDL cosimulation component, the results are converted back into ADS format and sent to the connecting ADS component.

You can specify the HDL simulation to run until the HDL simulator has no more events to process by specifying a negative iteration time. Using this method, the outputs are guaranteed to be stable since there are no more events left in the simulator that might change them. This method is less efficient than the fixed positive iteration time method, as the HDL simulator must be monitored to determine when all events have been processed. Also, it will not work for certain HDL models where some designs never run out of events, such as those with internal clock signals. When a negative iteration time is specified for a Verilog module, a VHDL wrapper is used to instantiate the Verilog module.