Time-Specified Signals in User HDL Code

When HDL code has internal clocks or time-specified signals (for example, wait statements in VHDL code) the HDL cosimulation may keep running until all the events in the user HDL code are processed. The number of events generated in user HDL code can be infinite (for example, when you have an internal clock).

You can avoid using an internal clock and use the ADS Clock instead (refer to the section Automatic Clock and Set Signals). If this is not possible, then infinite event processing can be avoided if you know how long the HDL simulation needs to run to complete the cosimulation, with all of the ADS iterations. Different simulators have different mechanisms to break a simulation after a certain simulation time. Here is an example using ModelSim:

1. Use the ModelSim simulator to create a file called test.do under your project's data directory. For example, test.do may look like this:

   run 11000
   quit -f

2. Set CmdArgs="-do test.do". This stops the simulation after 11000 nsec. (Refer to CmdArgs) on the HdlCosim component block.

The total run time can be calculated as equal to:

The number of ADS iterations (depends on the DF controller setup and the different sinks used in the design) multiplied by the IterationTime specified on the HdlCosim block.

Alternatively, you can also open the ModelSim UI mode and use multiple run 100 commands to see how long it takes before the message ADS has completed its simulation appears in the ModelSim UI. This time can then be used to create the test.do file.

Do not use the run-all command, which will process all the events in the HDL simulation.