CM_PatGen_169xx_Sink

Description: Downloads data to a pattern generator module housed in a 169xx mainframe
Library: Instruments
Class: SDFCM_PatGen_169xx_Sink

Parameters

Name	Description	Default	Unit	Type	Range
InstrumentHostname	Logic Analysis System hostname or IP address	la16900.wlv.agilent.com		string
InstrumentSetupFile	name of instrument state file			filename
ModuleName	name of the PattGen module to be used	My 16720A-1		string
BusSignalNames	names of bus signals in analyzer memory	MyBus1		string array
Start	sample number to start data recording	DefaultNumericStart		int
Stop	sample number to stop data recording	DefaultNumericStop		int
PGBFileName	name of pattern generator binary file	PattGen.pgb		filename
OverwriteExistingFile	overwrite if file exists: NO, YES	YES		enum
OutputMode	output channel mode: HalfChannel, FullChannel	HalfChannel		enum
ClkSource	clock source: Internal, External	Internal		enum
IntClkFrequency	internal clock frequency	180e6	Hz	real	(1, 300e6)
ClkOutDelay	delay the clock by multiple of 500 ps	0		int	(0, 14)
RunAfterLoading	clock data out of pattgen after download: NO, YES	YES		enum
RunMode	cycle through data once or repeat data: SinglePass, Repeat	Repeat		enum
InitSequenceFile	text file containing initial sequence data			filename
ControlSimulation	control simulation: NO, YES	YES		enum

Pin Inputs

Pin	Name	Description	Signal Type
1	input		multiple fix

Notes/Equations

1. The CM_PatGen_169xx_Sink model collects data from an ADS Ptolemy simulation and downloads the data into a Pattern Generator module residing in a 169xx Logic Analysis (LA 169xx) mainframe.

   Note The notation LA 169xx mainframe is used here to represent all Agilent 16900-series logic analysis systems and 1680/1690-series logic analyzer mainframes. A 169xx Logic Analysis mainframe is essentially a Windows XP computer housed in a modular frame with slots that accept measurement (Analyzer) and stimulus (Pattern Generator) plug-in cards. For more information regarding logic analysis systems, options, and modules, visit the website http://www.agilent.com/find/logic.

2. CM_PatGen_169xx_Sink uses the Agilent Connection Manager (CM) architecture to communicate with the instrument. Compared to other CM-based ADS Ptolemy instrument link models, this component has notable differences that are described here.
   CM_PatGen_169xx_Sink communicates with the instrument by using the CM server to load a COM Automation Server that is pre-installed on LA 169xx mainframes (as part of the Agilent Logic Analyzer application.) The COM object provides a mechanism for controlling the Agilent Logic Analyzer application from remote computers on the LAN. To enable CM_PatGen_169xx_Sink to communicate with an LA 169xx mainframe, install the CM server on the LA 169xx mainframe itself.
   For details regarding installing the CM server on a Windows XP PC, refer to Installing Connection Manager Server on Windows in the Windows Installation documentation.
   Note that also the Agilent Logic Analyzer application can be installed and used on a Windows XP/2000 computer for remote access of 16900- or 1680/1690-series logic analyzers on the network, or for offline analysis of data captured on 16900-, 1680/1690-, or 16700-series logic analyzers. In this setup, you must install the CM server on the same PC on which the Agilent Logic Analyzer application resides. This documentation refers to such a Windows XP/2000 computer as the LA 169xx mainframe and its file-system as the LA 169xx mainframe file-system, although it could be a standalone Windows XP/2000 computer running the Agilent Logic Analyzer application that emulates a LA 169xx mainframe.
   CM_PatGen_169xx_Sink does not enable interactive instrument selection using the Remote Instrument Explorer (a feature common to many CM-based instrument link models). This restriction is due to the nature of IO connectivity options available in the LA mainframes that the model interacts with.
3. Prerequisites for using CM_PatGen_169xx_Sink are:
   • An LA 169xx mainframe with the Agilent Logic Analyzer application installed (Refer to note 1 for the definition of an LA 169xx mainframe.)
   • An active Connection Manager server instance installed and running on the LA 169xx mainframe.
   • Network connectivity over the LAN from the workstation running ADS to the LA 169xx mainframe.
4. InstrumentHostname specifies the DNS hostname or IP address of the LA 169xx mainframe to be used.
5. InstrumentSetupFile optionally specifies an LA 169xx mainframe state file that should be loaded before simulation begins. The LA 169xx mainframe enables you to save the current instrument state and/or data into a file on its file-system. Any file path specified in InstrumentSetupFile must be relative to the instrument's file system. If a full path is not provided, the program assumes that the file exists in the default config directory (usually C:\Documents and Settings\<username>\MyDocuments\Agilent Technologies\Logic Analyzer\config).
6. ModuleName specifies the name of the Pattern Generator module that you want to send data to from the simulation. In Module Name Example, the module name would be My 16720A-1.
   
   

   Module Name Example

7. BusSignalNames specifies a string array containing the names you want to assign to the individual bus signals. Each signal is defined to be the width of the corresponding fixed-point data value on the input pin. For example, to assign incoming data from 3 connections at the input pin to 3 corresponding bus signals as in BusSignalNames Example, set BusSignalNames = MyBus1 MyBus2 MyBus3.
   
   

   BusSignalNames Example

8. Signals are ordered from bottom to top on the schematic. To download more than one signal using the CM_PatGen_169xx_Sink, use a BusMerge component to control the order.
   For example, when using a BusMerge and BusSignalNames = MyBus1 MyBus2, the bottom input is assigned the bus signal name MyBus1.
9. Start specifies the sample number of the first simulation data point you want to propagate into the instrument.
10. Stop specifies the sample number of the first simulation data point you want to propagate into the instrument. Stop can be any valid integer greater than Start.
11. PGBFileName specifies the name of the file on the instrument file system that holds the sequence data. If a full path is provided, the path must be relative to the LA 169xx mainframe file-system.
12. OverwriteExistingFile = YES instructs the pattern generator module to overwrite an existing file on the LA 169xx mainframe file-system whose name matches PGBFilename. OverwriteExistingFile = NO forces a simulation error if a file name matching InstrumentSetupFile is already on the LA 169xx mainframe file system.
13. OutputMode specifies the mode to put the pattern generator in to clock the data out. OutputMode = FullChannel limits the data rate to a maximum of 180 MHz, but enables 48 channels per card. OutputMode = HalfChannel enables an output rate of up to 300 MHz, but limits the number of channels to 24 per card.
    
    

    Output Mode Selection

14. ClkSource specifies the clock source to be used (Internal or External as shown in Output Mode Selection) to pace the pattern generator when moving data from its internal memory to its data pins.
15. IntClkFreq, used when ClkSource = Internal, specifies the rate at which data is clocked out of the pattern generator data pins.
16. ClkOutDelay specifies the positioning of the output clock relative to data signals. Setting this to a value greater than 0 increments the clock delay by the value multiplied by 500 ps.
17. RunAfterLoading specifies (NO, YES) whether you want to clock data out of the pattern generator after downloading data.
18. RunMode, used when RunAfterLoading = YES, specifies whether the pattern generator should clock one cycle of data from its data pins (RunMode = SinglePass) or cycle the main sequence repetitively (RunMode = Repeat).
19. InitSequenceFile specifies a filename that holds the data defining the initial sequence to be played prior to clocking the main sequence. The text file holds one integer value per line you want in the initial sequence; such a file can be generated using the Printer component in ADS Ptolemy. Note that ideally, the width of the integer data should be the same as the total width of the incoming data for all bus signals defined. However, because the incoming data could be wider than the maximum number of bits that can be represented by an integer, the vectors in the init sequence is zero-padded up to the required width.

    Important The number of data points specified in the init sequence file must be a multiple of 4 in half-channel mode and a multiple of 2 in full-channel mode. If this condition is not met, the additional data points in the file are discarded and a warning stating the same is generated during simulation.

20. ControlSimulation is used to specify (NO, YES) whether this component is to control the simulation lifetime.
21. CM_PatGen_169xx_Sink has a fixed-point multi-input pin. Each incoming fixed-point data can be of arbitrary width, but the width must be constant over a simulation run. If the total bit-widths of incoming data corresponding to all specified bus signals is greater than the vector bit-width that can be supported by the Pattern Generator module, an error is reported.
    When multiple bus signals are defined, incoming data is packed together without leaving any gaps between the bus signals. The bits are always packed starting from the most significant bit on the Pattern Generator.
    For example, in Bus Signals Are Packed Consecutively Across Byte/Slot/Pod Boundaries the incoming bus signal data widths for bus signals MyBus1, MyBus2, and MyBus3 are 12, 5, and 9, respectively. Bus Signals Are Packed Consecutively Across Byte/Slot/Pod Boundaries shows that bus signal assignments begin from the highest available slot (slot A in this example) on its highest available pod number (pod 6 in this example).
    
    

    Bus Signals Are Packed Consecutively Across Byte/Slot/Pod Boundaries

22. To access example designs that use this model, from the ADS Main window, choose File > Example Project > Instruments > CM_LA_169xx_prj.