PatGen_16720A_Sink

Description: Agilent 16720A Pattern Generator
Library: Instruments
Class: SDFPatGen_16720A_Sink

Parameters

Name	Description	Default	Unit	Type	Range
Interface	IP address	192.0.0.1		string
Login	Login name and password separated by colon	anonymous:ads		string
Slot	Slot of pattern generator card in mainframe	A		string
Start	Sample number to start pattern recording	DefaultNumericStart		int
Stop	Sample number to stop pattern recording	DefaultNumericStop		int
Labels	Labels for data	A		string array
ChannelMode	Full or Half channel mode: Half, Full	Full		enum
ClkSource	clock source for pattern generator: Internal (see IntClkFreq), External (frequency <= 50MHz), External (50MHz < f <= 180MHz), External (frequency > 180MHz)	Internal (see IntClkFreq)		enum
IntClkFreq	internal clock frequency	10e6	Hz	real

Pin Inputs

Pin	Name	Description	Signal Type
1	data	input data	multiple fix

Notes/Equations

1. The PatGen_16720A_Sink model collects bit sequences from a simulation and downloads them to a 16720A pattern generator module that is plugged into any of the 16700 series of logic analyzers.
2. Prerequisites for using the PatGen_16720A_Sink are
   • 16720A Pattern Generator; for information, visit the website http://www.agilent.com/find/xbv_pro_16720a.
   • 16700B Logic Analysis System; for information, visit the website http://www.agilent.com/find/xbv_pro_16700b.
   • LAN connectivity from your workstation to the Logic Analysis System mainframe. For detailed setup information, refer to Configuring the Server IO on the PC in the Connection Manager documentation.
3. This model programs the 16720A to output each of the model inputs as a separate labelled sequence. The 16720A sequences have the same bit width as the model's inputs, and these are named according to the Labels parameter.
4. The Interface parameter identifies the Logic Analysis System mainframe that contains the Pattern Generator as one of its modules. Set the Instrument parameter to the DNS hostname or IP address of the Logic Analysis System.
5. If you are using secure mode on your logic analyzer, set the Login parameter to a valid user and password that are separated by a colon. If you are using insecure mode, the default Login setting of anonymous:ads is fine.
6. The Slot parameter specifies the slot (A to J) in which the 16720A resides. The pattern generator in this slot must be activated before this instrument link can be used.
7. The Start and Stop parameters (as with all sinks) specify how much data to collect.
8. The Labels parameter names the signals input to PatGen_16720A_Sink. The same labels are assigned to the signals inside the 16720A. Use a minus sign as the first character of a label to set negative polarity for that signal.
   Labels are assigned in the same order as signals are connected. If you connect more than one signal to PatGen_16720A_Sink, use a BusMerge component to control the order. Remember that signals are ordered from bottom to top on the schematic. For example, when using a BusMerge4, the Labels format is Labels = {"A", "B", "C", "D"}, where the bottom input is A.
9. The ChannelMode parameter programs the 16720A to half- or full-channel output mode. Half channel mode enables a higher data rate of up to 300 MHz, but with only 24 channels; Full channel mode limits the maximum data rate to 180 MHz but enables use of all 48 channels.
10. The ClkSource and IntClkFreq parameters specify how to clock the data. For internal clocking, set ClkSource to Internal, and set IntClkFreq to the desired period. For external clocking, set ClkSource to the external setting corresponding to the external clock period.
11. Multiple pattern generator models can be plugged into the same mainframe.
12. To access example designs that use this model, from the ADS Main window, choose File > Example Project > Instruments > PatGen_prj.