About Netlist Translator for SPICE and Spectre

Spectre is an EDA (Electronic Design Automation) tool produced by Cadence Design Systems, Inc. The Simulation Program with Integrated Circuit Emphasis (SPICE) was developed at University of California Berkeley and has been commercialized and modified by a large number of vendors. It has also been adopted and modified by electronics companies for their own in-house use. Spectre and SPICE are used by engineers throughout the world for simulating circuits of all types. Many designers and companies have large investments in existing subcircuits or device models described by Spectre and SPICE netlists that they want to use with the Advanced Design System (ADS) from Agilent Technologies.

Advanced Design System

Advanced Design System has been developed specifically to simulate the entire communications signal path. This unique solution integrates the widest variety of proven RF, DSP, and electromagnetic design tools into a single, flexible environment. Building on years of expertise developing new technologies for our EDA tools, such as Series IV and MDS, Advanced Design System provides a broad range of high-performance capability. This makes it easy to explore design ideas and model the electrical and physical design of the best candidates.

Netlist Translator

Providing the ability to simulate a Spectre or SPICE netlist in ADS is a fundamental purpose of the Netlist Translator. The Netlist Translator is an ADS tool that enables you to import netlists into schematics and/or netlists for use with the ADS simulator.

Since Spectre, SPICE, and ADS simulators use different simulator technology, there may be incompatibilities between your original file and the resultant ADS file that the translator is unable to resolve. The incompatibilities may show up as import errors, simulation errors or differences in simulation results.

Every attempt has been made to record these inconsistencies in the translator log file, nettrans.log. Detailed information in this manual will help you identify and understand these limitations.

Major Benefits

The Netlist Translator enables you to perform the following:

• Generate an ADS schematic from a Spectre or SPICE Netlist for use in circuit design and simulation.

• Generate an ADS netlist from a Spectre or SPICE Netlist for use in simulations.

• Translate model files to incorporate them into ADS Design Kits.

Major Features

Key features of the Netlist Translator include the following:

• Automatic ADS design generation that includes circuit schematic, required model definitions and circuit equations or a reference to an equivalent ADS netlist to be used directly in simulation.

• Translation of component and model parameters to equivalent ADS parameters. In some cases this requires additional equations if the parameters do not translate directly. Parameters that cannot be translated are listed in the translator log file, nettrans.log.

Supported SPICE and Spectre Dialects

The Netlist Translator supports several SPICE dialects that are widespread throughout the electronics industry. The following table lists the five main dialects supported by the translator.

Supported SPICE and Spectre Dialects

Name	Manufacturer	Version
Spice2	UC Berkeley	2G6 (1981)
Spice3	UC Berkeley	3F3 (1993)
PSpice	Cadence	9.9.2 (August 2001)
HSpice	Avanti/Meta Software	v2003.3 (March 2001)
Spectre	Cadence	IC 5.1.41, Open Access 5.1.41, and Open Access 5.2.51

Note For translation purposes, Spice2 and Spice3 are almost identical and are referenced in this manual as Spice2/3.

General Process

The main objective of using the Netlist Translator is to import your Spectre or SPICE netlist into ADS. This enables you to simulate your design using the powerful tools provided by ADS. The following figure shows a simplified task flow for using the Netlist Translator.

Simplified Task Flow

What's in this Manual

The goal of this manual is to help you get started, provide relevant examples that teach you how to use the software, assist you in analyzing your translation and show you where you can get more information as you need it.

• Importing a Netlist File provides detailed instructions on using the Netlist Translator's user interface to import a netlist file into an ADS schematic or to an ADS netlist. Several example Spectre and SPICE netlists are used to help you understand and practice using the translator.

• Advanced Methods for Importing Files provides detailed instructions for advanced users who want to understand how to use the command line options that are available within the Netlist Translator. Additional information is provided to help with customizing components and other unique situations.

• Simulating the Translated Netlist provides general information on setting up, performing and analyzing a simulation using Advanced Design System. References to more detailed information are also provided in this chapter.

• Comparing Results provides information on comparing the output of your translation to your original netlist file. This chapter points out some specific details to look for when comparing your results.

• Troubleshooting provides helpful information on debugging imported designs and includes information on error and warning messages. Some known problems are described and solutions are included where available.

• Translating a Device provides detailed device translation information for individual components.

• Translating a Model provides detailed model translation information for individual models.

• User Defined Models and Parameter Mapping Rules provides information on adding your own unique models to ADS.

• Translating Commands and Functions provides information on the various commands and functions supported by the Netlist Translator.

About Design Translation and Verification

Design translation can be a very complicated process. It is important to understand that it is rarely, if ever, a push-button utility. Before starting a translation, you should become familiar with all parts of your design and be prepared to spend adequate time to ensure that all parts are translated correctly. After the initial translation is complete, additional work may be required to understand model differences. Verification and debugging the translated design may involve breaking a complex design down into smaller pieces to test simulation of small circuits before attempting to simulate a large design.

The support staff at Agilent Technologies can assist you in this process, but should not be expected to perform a complete translation and simulation. Please plan your project accordingly, allowing sufficient time in your schedule to use this tool as it is intended − as a tool to assist in the transfer of design information from one system to another.