Cosimulation with Analog-RF Systems

Simulation of behavioral DSP designs along with analog/RF circuit designs is critical to the success of the integrated components, devices, and subsystems used in today's wireless applications. The need to verify the impact of real-world analog/RF issues on the DSP algorithms and vice versa in a tightly integrated environment is highly desirable.

For designs of low complexity, it is possible to use separate simulators for the signal processing and analog/RF portions and then integrate the results. However, today's state-of-the-art designs using a mix of analog/RF and dedicated on-chip DSP blocks require high levels of integration at the two-environment boundary. Advanced Design System cosimulation between signal processing and circuits addresses this need. ADS Ptolemy provides the signal processing simulation, while the analog/RF simulation is provided by either the Circuit Envelope or High-Frequency SPICE (Transient) simulators.

Other types of cosimulation include placing MATLAB components or HDL blocks in a signal processing simulation. This topic describes cosimulation with analog/RF systems.

Note For information on A/RF cosimulation with Cadence refer to the Cadence Library Integration documentation. For specific details, see Running a DSP and Analog - RF Cosimulation with RFIC Dynamic Link.

The following figure shows a mixture of RF circuitry and DSP components. ADS provides a variety of analog/RF circuit simulators, including Linear, Harmonic Balance, Circuit Envelope, High-Frequency SPICE, and Convolution.

Note Circuit Envelope and High-Frequency SPICE simulators are included with some, not all, ADS suites.

For signal processing simulation, ADS Ptolemy is used. Only circuits simulated with either Circuit Envelope or High-Frequency SPICE can be instantiated as a subnetwork and included in a signal processing schematic. These circuit blocks can then be simulated along with signal processing components. The steps needed for cosimulation are described in the next section.

Cosimulation: Different Design Portions Simulated by Different Simulators in the Same Schematic

Setting Up the Analog/RF Circuit Schematic

Diode Rectifier Circuit Design Used in Cosimulation

To create circuit designs for cosimulation.

1. In the analog/RF circuit Schematic window, create a circuit schematic that includes a simulation component for either Circuit Envelope (called ENV) or High-Frequency SPICE simulation (called TRAN).
2. Generally, use Circuit Envelope for an RF simulation and High-Frequency SPICE (transient) for a baseband simulation.
3. Do not use Envelope and Transient simulators in the same design; if you want to keep both controllers in a design use activate/deactivate.
4. Add ports to your design.
5. Save your design.

In the previous figure, a diode rectifier is set to be simulated with the Circuit Envelope simulator. Next, we will place this subnetwork in the signal processing schematic where it will be represented as a block.

Setting Up the Signal Processing Schematic

Signal Processing Design Using Circuit Shown in Previous Figure

To create signal processing designs for cosimulation:

1. To place the circuit subnetwork(s) you have already created in the signal processing schematic, choose Component > Component Library. Your opened projects are listed at the top of the list. Circuit projects have (A/RF) at the end.
2. Choose the circuit design you want and place it in your signal processing schematic.
3. Add the signal processing components.
4. Add the signal processing controller(s).
5. Connect the circuit design to the signal processing components.
6. For cosimulation with the Circuit Envelope simulator, see Circuit Simulation Controllers.
7. If your circuit subnetworks have feedback loops between them, see Feedback Loops.
8. If the input signal into the circuit subnetwork is not of type Timed, see Numeric-to-Timed Converters.
9. Select the initialization method of the circuit inputs in the Signal Processing DF controller; see DF (Data Flow) Controller.
10. Start the simulation.

Circuit Simulation Controllers

As stated earlier, ADS Ptolemy can cosimulate with only the Circuit Envelope or High-Frequency SPICE simulators. Any circuit simulation control components other than ENV or TRAN (such as for harmonic balance or S-parameter simulation) are ignored in the cosimulation from the signal processing schematic.

Numeric-to-Timed Converters

Both Circuit Envelope and Transient simulators deal with time-domain signals. Therefore, signal processing components connected to the circuit subnetwork must be the timed type. If the input component (connecting signal processing components to the circuit) produces numeric data, place an appropriate numeric-to-timed converter (such as float-to-timed or complex-to-timed) in your schematic. These components (located in the Signal Converters library) ensure that the input into the circuit subnetwork is in the time domain. Refer to Time Converters for more information.

Automatic Verification Modeling (Fast Cosimulation)

Automatic Verification Modeling is a simulation mode that can significantly accelerate formerly lengthy cosimulations of Analog/RF circuits. You can enable Automatic Verification Modeling in the Circuit Envelope Simulation Controller. When enabled, this mode characterizes an analog subcircuit into a behavior model, then the model is used to predict the response of the subcircuit at each time point. For details about Automatic Verification Modeling, see Automatic Verification Modeling.

The following steps demonstrate how to enable the fast cosimulation mode using PtolemyDocExamples/AVM_prj from the examples directory:

1. In the ADS Main window, choose File > Copy Project. This opens the Copy Project dialog box.

   Note On UNIX platforms, you must copy an example project to a directory for which you have write permission. On Windows platforms, you can work directly in the Examples directories; however, it's better to copy examples to a working directory.

2. In the From Project area, click Example Directory, then click Browse. The Copy From File Browse dialog box opens showing the Examples directories.
3. Select the PtolemyDocExamples directory.
   On Windows, the list of available projects appears in the list.
   On UNIX, click Filter to see the list of projects.
4. On Windows, select AVM_prj . Click OK .
   On UNIX, in the Files list, select AVM_prj. Click OK.
5. In the To Project area, click Startup Directory or Working Directory to select the destination directory for the copied project. Click Browse to select another directory.
6. Select Copy Project Hierarchy to enable this option which ensures all appropriate directories and files are copied.
   Select Open Project After Copy to enable this option which opens the project immediately after copying.
7. Click OK to copy the project and close the dialog box.
8. In the ADS Main window, choose File > Open Project to open the Open Project dialog box. In the Directories list, select the directory to which you copied the example.
   On Windows, select RectifierCosim_prj, then click OK .
   On UNIX, double-click RectifierCosim_prj in the Files list.
9. In the Main window, choose File > Open Design to open the Open Design dialog box. In the Designs list, double-click TestMixer.dsn.
10. In the Schematic window, select DUT_Mix_sub, and push into its hierarchy, then push into the DUT_Mixer hierarchy as shown in the following figure.
11. In the DUT_Mixer, double-click the Envelope simulation controller to open its setup dialog. Select the Cosim tab, and click Enable AVM (Fast Cosim) to enable the mode.

    Note To enable AVM (Fast Cosim) directly on the schematic, click the Display tab on the Circuit Envelope setup dialog. Enable the ABM_Mode parameter. On the schematic, set ABM_Mode=yes to enable the mode; set ABM_Mode=no to disable the mode.

    

    Pushing into TestMixer.dsn Hierarchy to Enable AVM (Fast Cosim)

Clustering of Circuit Subnetworks

Clustering is the process of defining the boundaries of the signal processing and analog/RF simulators. Initially, this boundary is defined by circuit schematics, where you define the circuit subnetworks and then make an instance of those on the Signal Processing schematic. However, there is a bit more to clustering than what is on the two schematics.

Circuit subnetworks directly connected in the Signal Processing schematic are automatically clustered and treated as one circuit subnetwork, as shown in the following figure. Therefore, use only one circuit simulation control component in either of the two (or more) directly connected subnetworks.

Connected Subnetworks Treated as One

Connected Circuit Subnetworks

When two circuit subnetworks defined on two different circuit schematics are connected on a Signal Processing schematic, the two circuit subnetworks are clustered into one (this is done transparently and should not concern the user). However, if each of these two circuit subnetworks use their own simulation controller, then the circuit engine would not know which one to choose for simulation and would result in an error message.

Connected Resistors

Another aspect of clustering is when circuit components available on the Signal Processing schematic (resistors in the first release of Advanced Design System) are connected to a circuit subnetwork. In this case, such resistors will be absorbed into the circuit subnetwork during the clustering and will be simulated by the circuit engine as part of circuit subnetwork.

Feedback Loops

Circuit subnetworks that form a feedback loop via signal processing components require a delay component in the feedback loop to facilitate the signal processing simulation scheduling, as shown in the following two figures. If such a delay is not present, an error message will be issued. To have the program automatically insert the delay, you must edit the DF (data flow) controller parameters. To do this, double-click the controller, choose the Options tab, then select Resolve deadlock by inserting tokens from the DeadlockManager drop-down list. For more information about deadlocks, refer to Deadlocks.

Feedback Loop Before Delay Added by Program

Feedback Loop After Delay Added by Program (Delay Not Shown on Schematic)

Named Connections and Measurements in Circuit Designs

Named connections and measurements included in the circuit schematic design (such as for a voltage) are ignored in cosimulation. The only results you get from a cosimulation are obtained from the Signal Processing schematic using Sink components or Interactive Components and Displays items.

Circuit Envelope Specific Rules

The output of the Circuit Envelope simulator is a collection of time waveforms, each at a different fundamental frequency. You must select the waveform you want by specifying this fundamental frequency. You do this by choosing the EnvOutSelector or EnvOutShort component from the Circuit Cosimulation library. Refer to EnvOutSelector and EnvOutShort Components for more information. Place this component at all circuit subnetwork output ports in the Signal Processing schematic.

Circuit Envelope simulation requires that many parameters be set up in the circuit schematic. For more information, refer to Advanced Design System's Circuit Envelope Simulation documentation. For cosimulation, the key parameter is the Step parameter. This is the time step used by the simulator, and can be set equal to or less than the time step at the connecting port in the signal processing schematic design. Other important parameters for cosimulation (especially nonlinear designs) are MaxOrder, Freq[], and Order[]. Make sure that the OutFreq parameter specified at the EnvOutSelector or EnvOutShort component is among the fundamental frequency or harmonics specified by the Circuit Envelope controller.

To enable or disable the addition of noise from the Circuit Envelope components, use the Turn on all noise parameter in the Env Params tab. For cosimulation, the Nonlinear noise button, the Small-signal button, and their corresponding tab pages should not be used as they are not used during cosimulation. Note that explicit noise sources, such as _V_Noise_, are always on. The Turn on all noise enables or disables only the noise generated by non-source models, such as the resistors, lossy transmission lines, and transistors.

The amplitude of these noise sources is determined by the Circuit Envelope bandwidth, which is determined by 1/(Time Step). Normally, this Circuit Envelope timestep would be the same timestep as that used by Ptolemy, so the total noise bandwidths are the same. However, for designs where the Ptolemy waveform is changing too rapidly for the analog simulation and the user has reduced the Circuit Envelope timestep, then the Circuit Envelope noise bandwidth also increases. Depending on the circuit behavior, this broader bandwidth noise may appear at the circuit output, where it is now effectively sampled by the EnvOut element. This sampling will then alias all the higher bandwidth circuit noise, and result in a higher noise density within the Ptolemy noise bandwidth. If this is not the desired simulation behavior, then a filter may need to be placed at the circuit output. Of course, this will also filter any signals being passed back to the Ptolemy simulation.

Transient Simulation Specific Rules

When cosimulation with ADS Ptolemy and the Transient simulator is required, the circuit schematic must have a Transient (Tran) simulation controller (a transient simulation component ). No explicit user setting is required for the Tran controller; that is, the default parameters will work for cosimulation. However, the Tran controller's Freq [x] parameter is required when there are any frequency-dependent sources. The Freq [x] parameter specifies the fundamental frequency.

There is a difference between ADS Ptolemy and the Transient simulator regarding how they treat signals at time=0- (before t=0) that may cause unexpected results; they have different simulation assumptions for time=0-. ADS Ptolemy assumes signal states at time=0- are zeros, while the Transient simulator assumes signal states at time=0- the same as time=0. For a circuit with a given input signal stimulus to give the same response for both Ptolemy/Transient cosimulation and for Transient simulation alone, the circuit signal stimulus for the Ptolemy/Transient cosimulation must have a zero value at time=0. If the signal stimulus into the circuit during a Ptolemy/Transient cosimulation is not zero at time=0, then the cosimulated Transient simulator will result in output signals that are not expected when compared to a Transient-alone simulation. To force the circuit input to be zero during a Ptolemy/Transient cosimulation, the workaround is to change the CktCosimInputs setting on the Options tab of the DF (data flow) controller (refer to Options Tab for details).

Nested Simulation Approach

ADS cosimulation is based on a nested simulation approach. In this use model, you first create your circuit designs on the circuit schematic. This circuit design can be tested using appropriate circuit sources and measurements with either the Circuit Envelope or High-Frequency SPICE simulators. Once the circuit design has been verified, ports to be interfaced with the signal processing design are identified and placed. Next, you place an instance of the design on the Signal Processing schematic and connect it to the other blocks. The combined schematic design can now be simulated.

Signal Processing Model of the Circuit Network

ADS Ptolemy uses a data flow simulation approach, and this simulation is controlled using the DF (data flow) controller component. To understand this chapter, you need to be aware that this simulation is based on invoking a schedule . A schedule tells the simulator engine to fire components in a certain order and with a certain frequency. A simulation is typically a repetition of a schedule many times.

From the data flow engine perspective, a circuit subnetwork on the Signal Processing schematic is just a component with a certain number of input and output ports. This circuit subnetwork is part of the schedule determined by the data flow engine. It would be fired just like any other component according to the schedule, and as many times as required. Every time the circuit subnetwork is fired, the circuit simulator (designated by the simulation controller on the circuit schematic) continues to carry on the simulation based on the input it receives from the signal processing interface. Once the circuit simulator completes its analysis, it passes the simulation results back to the signal processing interface. This cycle repeats as many times as the scheduler requires. The duration of the circuit simulation each time it is invoked is determined by the time step provided by the connecting signal processing component at the input interface to the circuit subnetwork.

Circuit Model of the Signal Processing Network

From the circuit simulator engine point of view, the signal processing input interface is viewed as an ideal (0 ohm impedance) source. The more ports at the input interface to the circuit, the more ideal sources there will be feeding the circuit subnetwork. At the output interface of the circuit, there would be a node where the results are shared with the connecting signal processing component.

Interface Issues

At the interface boundary of the signal processing and analog/RF circuit simulators, there needs to be an exchange of information. The semantics and fundamentals of simulation in the two application areas are quite different and therefore, you need to understand these differences for proper use. The following sections outline the most important aspects of this interface.

Time Step

Time samples for signal processing are one fixed time step apart. However, both Envelope and Transient simulators define the time step in the simulation controller with various options.

The Transient Simulator controller component has several parameters, including Start time, Stop time, Min time step, and Max time step (see the Time Setup tab). In addition, the Integration tab contains a time step control method parameter with Fixed, Iteration Count, and Truncation Error options. For more information, refer to Transient and Convolution Simulation.

For cosimulation with the Transient simulator, keep in mind one key issue: The Transient simulator may need time steps smaller than ADS Ptolemy's Time Step to satisfy its own setup requirements. In addition, the Transient simulator, when needed, will take additional time steps to match the time points in the signal processing simulation. Only time steps that match the signal processing time points will be passed on to ADS Ptolemy.

Note For all practical purposes, the only parameter that may concern the cosimulation user is the Max time step. Other parameters in the Transient Simulation control component can remain at default values. For the Circuit Envelope simulator, the time step parameter in the ENV Simulation controller component should be set equal to or less than the Time Step at the signal-processing-to-circuit interface. Depending on the Time Step value you set, the simulator will set the internal Circuit Envelope time step to either the Ptolemy time step value, or to an integer sub-multiple of this value. Time step values less than the Ptolemy time step value are sometimes required to achieve the desired accuracy, due to rapidly changing signals and the integration required for capacitive and inductive components. If the Circuit Envelope value is less than one-tenth of the Ptolemy time step value, a warning is generated to alert you to this so you can avoid inadvertent small time step values that might unnecessarily be slowing the cosimulation.

Note The Stop time for the simulation is determined by the Signal Processing Data Flow controller and/or Sinks. The Circuit Envelope Stop time does not affect the duration of the cosimulation. The Stop Time value is used in a few models and, ideally, should be set to reflect an approximate stop time range. As an example, for explicit Analog/RF Noise sources that have a user-specified baseband frequency response, this stop time value is used to determine the maximum duration of the pre-computed random noise sequence. Presently, the stop time is limited to about 2.1M (=2 21 ) times the time step value. If the cosimulation runs longer than this, then this noise data is repeated.

Delays in Feedback Loops

As stated earlier, Data Flow simulation requires that a Delay component exist in the feedback loops for proper activation of the schedule. Circuit subnetworks that form a feedback loop, for this same reason require a delay component in their path. Typically, a DelayRF component in such feedback loops will suffice. If such a delay does not exist, ADS Ptolemy will report a deadlock by default.

Time Converters

The common signal being exchanged between signal processing Data Flow components and the circuit simulators (Circuit Envelope and Transient) is a time-domain signal. All three engines, hence, deal with the notion of time step.

The signal entering the circuit subnetwork should be Timed. The Transient simulator deals only with real-baseband time-domain signals while Circuit Envelope can handle both baseband and complex envelope timed signals.

If the signal entering into the circuit subnetwork is not Timed (that is, the signal is Numeric), you should place a FloatToTimed, FixToTimed, IntToTimed, or CxToTimed converter to accommodate the conversion. Although ADS Ptolemy will place appropriate converters when they do not exist, it is always a good practice to explicitly place and connect these converters in your design. This will ensure that the input parameters into the circuit subnetwork are correct, as well as helping to debug possible errors that may occur.

Carrier Frequency

In the case of cosimulation with the Circuit Envelope simulator, the timed signal entering the circuit subnetwork is typically a carrier-modulated timed signal. This means that timed data has an F _c field that is passed to the Circuit Envelope simulator, which is needed by the simulator. The Circuit Envelope simulator, depending on a particular design, will generate a number of time-domain waveforms, each associated with a carrier (harmonic) frequency. Since ADS Ptolemy supports only one carrier frequency at each node, you need to select which one of the waveforms you desire in the signal processing portion of the design. This is done by placing a Circuit-Envelope specific component described next.

EnvOutSelector and EnvOutShort Components

When cosimulating with the Circuit Envelope simulator, additional information is needed for proper cosimulation. This is done by connecting an EnvOutSelector or EnvOutShort component (from the Circuit Cosimulation library in the Signal Processing schematic) to each output port of the subnetwork design.

The EnvOutSelector component acts as an open, blocking everything connected to its output from loading the circuit. If such loading is desired, use the EnvOutShort component. The EnvOutShort component acts as a short and therefore loads the circuit with the connecting Signal Processing components.

The EnvOutSelector and EnvOutShort components have a parameter called OutFreq . OutFreq specifies which waveform is selected from the time-domain waveforms at the output of the Circuit Envelope simulator. OutFreq has the following options:

• Lowpass-selects the time-varying DC component.
• Bandpass-(default) lets you specify any frequency.
• Allpass-forms the composite (baseband) signal.

One or more EnvOut components (EnvOutSelector and EnvOutShort) can be connected to each output port of a circuit subnetwork as illustrated in the following figure. All waveforms generated by the Circuit Envelope simulator can be accessed in a Signal Processing schematic.

EnvOut Components (EnvOutSelector or EnvOutShort) at each Circuit Subnetwork Output Port

When an EnvOutSelector or EnvOutShort component is used with a design simulated by the Transient simulator, their effect is an open or a short, respectively. Otherwise they do not affect transient cosimulation designs and can remain in place without any impact on the cosimulation.

Snapping Rule

In the Bandpass option of the OutFreq parameter, you can type in the desired fundamental whose time waveform you are interested in. If the frequency you specify does not exist in the list of fundamentals, the interface program will search and snap to the nearest fundamental. Anything within 0.01% of a fundamental will be snapped to that fundamental frequency. If the frequency specified in the Bandpass option of OutFreq is not within 0.01% of the fundamental, a default value of 100 MHz will be used and a warning message issued.

Troubleshooting Common Problems

While the cosimulation use model is intuitive, the following information will help you avoid errors.

1. Only the Transient and Circuit Envelope circuit simulators can cosimulate with ADS Ptolemy. Other circuit simulation controllers on the analog/RF schematic (such as S-parameter or AC) will be ignored in cosimulation.
2. Directly connected circuit subnetworks placed as instances on Signal Processing schematics are clustered together and should be considered as one circuit subnetwork. This means that if each of these subnetworks has their own circuit simulation controller, an error message will be issued. To avoid such problems you can either:
   • Deactivate all controllers but one on the circuit schematics.
   • Connect a signal processing component between the two circuit subnetworks, thereby preventing the two subnetworks from being clustered into one.
3. Resistor components that are part of hierarchical designs of timed components in the Signal Processing schematic will be absorbed into connecting circuit subnetworks by the program. If the EnvOutSelector component is used, the absorbed resistors will not load the circuit, since the circuit model is an open. If the EnvOutShort component is used, the absorbed resistors will load the circuit, and the results will be different by a scale factor.
4. Since resistors that are part of timed subnetworks are absorbed into connecting circuit subnetworks, you should avoid placing a sink or any other signal processing component directly at this port, when cosimulating with Circuit Envelope. If placed, an error message is issued, requiring an EnvOutSelector component to be placed. The reason for this condition is the fact that the sink now constitutes an output port from the perspective of the circuit subnetwork.
5. Writing a VAR in the analog/RF subnetwork to the dataset cannot be done using the Output tab on the Circuit Envelope Controller's setup dialog box, nor by using OutVar in the Data Flow Controller. It can be done by using the Output tab option in the top-level DF controller, or defining the VAR in the top-level DSP design.

Cosimulation Example

To illustrate cosimulation, we will use an example called RectifierCosim_prj.

Copying and Opening the Project

1. From the Main window, choose File > Copy Project. A dialog box appears.

   Note On UNIX platforms, you must copy the example project to a directory for which you have write permission. On Windows platforms, while you can work in the Examples directories, it is a good idea to copy examples to another directory.

2. In the From Project area, click Example Directory, then click Browse. The Copy From File Browse dialog box opens showing the Examples directories.
3. Select the /Com_Sys directory.
   On Windows, the list of available projects appears in the list.
   On UNIX, click Filter to see the list of projects.
4. On Windows, select RectifierCosim_prj. Click OK.
   On UNIX, in the Files list, select RectifierCosim_prj. Click OK.
5. In the To Project area, click Startup Directory or Working Directory to select the destination directory for the copied project. Click Browse to select another directory.
6. Select Copy Project Hierarchy to enable this option which ensures all appropriate directories and files are copied.
   Select Open Project After Copy to enable this option which opens the project immediately after copying.
7. Click OK to copy the project and close the dialog box.
8. In the ADS Main window, choose File > Open Project to open the Open Project dialog box. In the Directories list, select the directory to which you copied the example.
   On Windows, select RectifierCosim_prj, then click OK.
   On UNIX, double-click RectifierCosim_prj in the Files list.

Rectifier Schematic

The top level design RectifierCx_Tutorial, as shown in the immediately following figure, generates a complex modulated signal and sends that signal into a simple rectifier circuit.

Two identical instances of this rectifier circuit are created on a circuit schematic, one with a TRAN controller (rct_Tran), in the second figure below, and the other with an ENV controller (rct_Env), in the third figure below.

RectifierCosim Project Top-Level Schematic

Circuit Subnetwork with Transient Controller

Circuit Subnetwork with Circuit Envelope Controller

To view the circuit subnetworks from the top-level design, choose View > Push_Into Hierarchy or click the Push_Into Hierarchy button (down arrow) from the toolbar.

The circuit design in both rct_Tran and rct_Env is a simple diode with a shunt parallel RC attached to its output. Note the placement of ports and that rct_Env has an Circuit Envelope controller, while rct_Tran a Transient controller. The two circuit designs are then placed on the Signal Processing schematic.

On the Signal Processing schematic, the generation of complex modulated signals is accomplished via a RectCx component that generates a periodic pulse with a complex amplitude. This complex pulse is then fed into a CxToTimed component that effectively upconverts the signal. The TStep is set to 0.01 µsec and the carrier is at 11 MHz. This modulated RF signal is then split into two branches by a SplitterRF component and fed into the rct_Tran and rct_Env circuit subnetworks. In addition, there are TkPlot components (which display the simulation results) attached to the output of RectCx and CxToTimed to monitor the signal before simulation.

Since the TStep of the signal entering circuit design is at 0.01 µsec, the MaxTimeStep on the Transient controller is set to the same value. This value should always be smaller than or equal to the Signal Processing TStep. The other Time setup parameters, such as Start time and Stop time, are ignored in the Transient cosimulation. Note that the output of rct_Tran is directly fed into a TkPlot without an interface component.

Similarly for the Circuit Envelope simulator, the Step parameter of the simulation controller should be set less than or equal to the Signal Processing TStep. Other parameters of interest are Freq[], Order[], and MaxOrder, which specify the fundamentals and related harmonics to be analyzed. In this example, the fundamental of interest is Freq[1] = 11MHz and the MaxOrder and Order[1] are set to 5. Note also, that Freq[0] is the dc term that is always available.

Typically, there is only one EnvOut component ( EnvOutSelector or EnvOutShort ) attached to the Circuit Envelope subnetwork output, but in this example we have used three to show the different signals that can be selected from the Circuit Envelope output. Specifically, the OutFreq parameter is set to the Bandpass, Allpass and Lowpass options in the three instances. When Bandpass is selected, the dialog box changes so you can enter the desired fundamental frequency; in this case, OutFreq is set to 11 MHz. The output of EnvOutSelectors are then fed into three interactive TkPlot display components.
When we simulate this design, 6 TkPlot windows pop up, as shown next.

The plot Complex Bits displays the magnitude of the complex periodic pulse and the plot Rectifier Input depicts the pulse-modulated signal at 11 MHz.

The plot Transient Output is the rectified version of the modulated signal (note that there are no negative components in the signal), where the value of the time constant (RC) determines the degree of pulse fall-off. Note also that this output is a real-baseband signal and includes all the harmonics.

The allpass, lowpass, and bandpass output plots are shown next.