Manuals >Nonlinear Device Models Volume 1 >BSIM3v3 Characterization Print version of this Book (PDF file) 



Capacitance ModelPlease use the model bsim3_tutor_cv.mdl provided with the BSIM3v3 Modeling Package to visualize the capacitance model parameters. Load the file into ICCAP and run the different macros to see how certain parameters affect the device behavior of a deep submicron MOS transistor. The capacitance in a MOS transistor can be divided into three different parts:
These different parts of the capacitance of a MOS transistors are shown in Figure 97. The following three sections explain each type of capacitance and its implementation in the BSIM3v3 model.
Junction CapacitanceThe source/drainbulk junction capacitance can be divided into three components as shown in Figure 98. The calculation is shown for the drainbulk junction capacitance. The sourcebulk capacitance is calculated in the same way with the same model parameters. The overall junction capacitance C_{jdb} is given by:
C_{jbd} is calculated according to the following equation and is shown in Figure 99.
Peripheral sidewall capacitance C_{SW} along the field oxide (95) C_{SW} = (PD  W_{eff})C_{jbdsw}
C_{jbdsw} is calculated according to the following equation and is shown in Figure 100:
Peripheral sidewall capacitance C_{SWG} along the gate oxide (97) C_{SWG} = W_{eff}C_{jbdswg} C_{jbdswg} is calculated according to the following equation and is shown in Figure 101.
Extrinsic CapacitanceAs mentioned in the introduction to this chapter, the extrinsic capacitance of a MOS transistor consists of the following three components:
The contribution of these different components to the overall extrinsic capacitance is demonstrated in Figure 102 and Figure 103.
a) Fringing CapacitanceThe fringing capacitance of a MOS transistor consists of a bias independent outer fringing capacitance and a bias dependent inner fringing capacitance. In the present release of the BSIM3v3 model, only the bias independent outer fringing capacitance is implemented. Experimentally, it is virtually impossible to separate this capacitance with the overlap capacitance. Nonetheless if the model parameter CF is not given, the outer fringing capacitance can be calculated with the following equation: b) Overlap CapacitanceIn BSIM3v3 an accurate model for the overlap capacitance is implemented. In old capacitance models this capacitance is assumed to be bias independent. However, experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure, the bias dependence is the result of depleting the surface of the source and drain regions. Since the modulation is expected to be very small, this region can be modeled with a constant capacitance. However in LDD MOSFETs a substantial portion of the LDD region can be depleted, both in the vertical and lateral directions. This can lead to a large reduction of overlap capacitance. This LDD region can be in accumulation or depletion. In BSIM3v3, a single equation is implemented for both regions by using such smoothing parameters as Vgs_{overlap} and Vgd_{overlap} for the source and drain side, respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are reciprocal. In other words, Cgs_{overlap} = Csg_{overlap} and Cgd_{overlap} = Cdg_{overlap}. The model equations for the overlap capacitance are shown for the drain overlap capacitance and are identical for the source overlap capacitance: Overlap charge per gate width: for the measurement and simulation conditions given in Figure 102, this results in the overlap capacitance: The model parameter CGDO in Equation 100 can be calculated by the following equation: where DLC represents the channel length reduction in the BSIM3v3 capacitance model. Please see the next section for more details about DLC: Intrinsic Capacitancea) Geometry for Capacitance ModelThe BSIM3v3 model uses different expressions for the effective channel length L_{eff} and the effective channel width W_{eff }for the IV and the CV parts of the model. The geometry dependence for the intrinsic capacitance part is given as the following: L_{active} and W_{active} are the effective length and width of the intrinsic device for capacitance calculations. The parameter ΔL is equal to the source/drain to gate overlap length plus the difference between drawn and actual poly gate length due to processing (gate printing, etching, and oxidation) on one side. The L_{active} parameter extracted from the capacitance method is a close representation of the metallurgical junction length (physical length).
While the authors of the BSIM3v3 model suggest to use a parameter LINT for the IV model, which is different from DLC, other literature sources [3] propose that LINT should have the same value as DLC. This approach is also implemented in the BSIM3v3 Modeling Package to ensure that the extracted values of the channel length reduction are very close to the real device physics. Therefore, the channel length reduction LINT for the IV model will be set to DLC from the CV model extracted from capacitance measurements. b) Intrinsic Capacitance ModelThe intrinsic capacitance model that is implemented in the BSIM3 model is based on the principle of conservation of charge. There are a few major considerations in modeling the intrinsic capacitance of a deep submicron MOS transistor:
Therefore, this section presents no details about the intrinsic charge formulations. Please refer to the BSIM3v3 manual [1] for more information. Only the basic principles are described here. To ensure charge conservation, terminal charges instead of the terminal voltages are used as state variables. The terminal charges Q_{g}, Q_{b}, Q_{s}, and Q_{d} are the charges associated with the gate, bulk, source, and drain. The gate charge is comprised of mirror charges from 3 components:
The accumulation charge and the substrate charge are associated with the substrate node while the channel charge comes from the source and drain nodes: The inversion charges are supplied from the source and drain electrodes. The ratio of Q_{d} and Q_{s} is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (given by the model parameter XPART = 0, 0.5, and 1) which are the ratios of Q_{d} to Q_{s} in the saturation region. From these four terminal charges, 9 transcapacitances C_{(terminal,voltage)} are calculated inside the BSIM3 model as partial derivatives with respect to the voltages V_{gb}, V_{db,} and V_{sb}. The abbreviation can be interpreted as: The 9 transcapacitances previously introduced are shown in the following three plots for a simulation setup as shown in the following figure:
The Overall Capacitance in BSIM3In previous sections, the three components of the BSIM3 capacitance model were introduced. Now when an AC simulation is performed the capacitance, which can be measured at the terminals, is composed of different parts of junction capacitances, extrinsic capacitances, and intrinsic capacitances. The following figure shows, as an example, the capacitance components for the overlap capacitance between gate and bulk/source/drain as simulated according to the following circuit description:
The overlap capacitance C_Gate_SDB consists of: Other capacitances can be calculated in the same way. Please refer to the BSIM3 manual for more details. 


